39
Substrate-Induced Strain Engineering in CMOS Technology
in Figure 2.16, a thin Si spacer separating the two QWs is desirable as far as
mobility is concerned, but also, the QWs should be maintained uncoupled,
because such communication, i.e., the overlap of the carrier wave function,
will degrade the mobility. In the retrograde DQW of design II, the high-Ge
channel reaches strong inversion first, followed by the low-Ge channel, and
at higher gate biases the surface channel also inverts. The main conducting
channel is the high-Ge channel because it populates higher hole density.
Since this main channel is more buried than in SQW, it should come as no
surprise that hot-carrier degradation is further suppressed. It is expected
that the retrograde DQW structure will have a further improvement in
mobility, hot-carrier degradation, transconductance at low-voltage operation, and a reduced 1/f noise and random telegraph signals. Such a structure
may be suitable for analogue applications. Recently Si 1–x Ge x p-MOSFETS
with a retrograde double quantum well structure have been demonstrated
experimentally with improved performance.
The turn-on of the surface channel can be suppressed by thinning the Si cap
layer. In the case of SQW devices, the SQW channel comes closer to the gate
and an improved transconductance can be expected. However, the expected
gain in transconductance is not achieved in these devices due mainly to surface roughness and interface scattering. Also, SQW MOSFETs are susceptible to both hot-carrier degradation and mobility degradation. This trade-off
might be less problematic in the retrograde DQW device because the main
high-Ge channel is separated from the gate by the other low-Ge channel.
As for hole density, it has been reported that there is no improvement in the
retrograde DQW structure, compared to design I, which almost acts as a
SQW device.
The intrinsic material properties of Si 1–x Ge x , rather than shrinkage of
devices, make possible the achievement of performance enhancement in
these devices. Employment of <100> channel direction in a strained Si 0.8 Ge 0.2
p-MOSFET has demonstrated the substantial amount of hole mobility
enhancement, as large as 25%, and parasitic resistance reduction of 20%, compared to a <110> strained Si 0.8 Ge 0.2 channel p-MOSFET, which already has an
advantage in mobility and the threshold voltage roll-off characteristic over
the Si p-MOSFET. This result indicates that the <100> strained SiGe channel
p-MOSFET is a promising and practical candidate for realising high-speed
CMOS devices under low-voltage operation. In general, in comparison with
conventional Si MOSFETs, Si/Si 1–x Ge x /Si MOSFETs benefit from the following advantages: (1) higher channel mobility, (2) smaller width, i.e., higher
packing density, (3) higher transconductance and improved speed, (4) lowerpower-delay product, (5) better immunity to hot-carrier degradation, and (6)
reduced flicker and random telegraph noise.
SiGe technology, developed for over two decades, has been plagued by
the problem for device applications requiring a high Ge mole fraction. The
thermal stability of strained Si and compressively strained Si 1–x Ge x layers
is a major concern in many device structures. Consequently, the design
Substrate-Induced Strain Engineering in CMOS Technology
in Figure 2.16, a thin Si spacer separating the two QWs is desirable as far as
mobility is concerned, but also, the QWs should be maintained uncoupled,
because such communication, i.e., the overlap of the carrier wave function,
will degrade the mobility. In the retrograde DQW of design II, the high-Ge
channel reaches strong inversion first, followed by the low-Ge channel, and
at higher gate biases the surface channel also inverts. The main conducting
channel is the high-Ge channel because it populates higher hole density.
Since this main channel is more buried than in SQW, it should come as no
surprise that hot-carrier degradation is further suppressed. It is expected
that the retrograde DQW structure will have a further improvement in
mobility, hot-carrier degradation, transconductance at low-voltage operation, and a reduced 1/f noise and random telegraph signals. Such a structure
may be suitable for analogue applications. Recently Si 1–x Ge x p-MOSFETS
with a retrograde double quantum well structure have been demonstrated
experimentally with improved performance.
The turn-on of the surface channel can be suppressed by thinning the Si cap
layer. In the case of SQW devices, the SQW channel comes closer to the gate
and an improved transconductance can be expected. However, the expected
gain in transconductance is not achieved in these devices due mainly to surface roughness and interface scattering. Also, SQW MOSFETs are susceptible to both hot-carrier degradation and mobility degradation. This trade-off
might be less problematic in the retrograde DQW device because the main
high-Ge channel is separated from the gate by the other low-Ge channel.
As for hole density, it has been reported that there is no improvement in the
retrograde DQW structure, compared to design I, which almost acts as a
SQW device.
The intrinsic material properties of Si 1–x Ge x , rather than shrinkage of
devices, make possible the achievement of performance enhancement in
these devices. Employment of <100> channel direction in a strained Si 0.8 Ge 0.2
p-MOSFET has demonstrated the substantial amount of hole mobility
enhancement, as large as 25%, and parasitic resistance reduction of 20%, compared to a <110> strained Si 0.8 Ge 0.2 channel p-MOSFET, which already has an
advantage in mobility and the threshold voltage roll-off characteristic over
the Si p-MOSFET. This result indicates that the <100> strained SiGe channel
p-MOSFET is a promising and practical candidate for realising high-speed
CMOS devices under low-voltage operation. In general, in comparison with
conventional Si MOSFETs, Si/Si 1–x Ge x /Si MOSFETs benefit from the following advantages: (1) higher channel mobility, (2) smaller width, i.e., higher
packing density, (3) higher transconductance and improved speed, (4) lowerpower-delay product, (5) better immunity to hot-carrier degradation, and (6)
reduced flicker and random telegraph noise.
SiGe technology, developed for over two decades, has been plagued by
the problem for device applications requiring a high Ge mole fraction. The
thermal stability of strained Si and compressively strained Si 1–x Ge x layers
is a major concern in many device structures. Consequently, the design