36
Strain-Engineered MOSFETs
reduction in the traverse effective mass in strained Si 1–x Ge x layers. The compressive strain in the plane also lifts the degeneracy of the valence band, and
the HH band dispersion becomes LH-like, and therefore interband scattering is reduced. Increasing the Ge percent also results in further reduction of
the effective mass. For lateral transport, it is desirable to have a light in-plane
effective mass in order to enhance the carrier mobility. In a p-MOSFET with
such structures, an intrinsic buried Si 1–x Ge x channel is desirable to reduce the
Coulomb scattering of carriers by ionised impurities. On top of this layer a thin
cap layer of Si is deposited to facilitate growing the gate oxide (see Figure 2.14).
Thermal oxidation of strained Si 1–x Ge x is not viable and results in a pile-up of
Ge at the dielectric/SiGe interface with an increase of interface state density,
thus degrading the mobility. It should be noted that one of the advantages of
buried channels is that they provide more immunity to hot-carrier degradation because carriers have to travel longer distances to reach the gate dielectric.
The transconductance reduction in buried channels is already compensated
for by the higher hole mobility in strained SiGe materials, as we explained
earlier, and also by avoiding the Si/SiO 2 interface roughness scattering.
2.8.3 Double Quantum Well p-MOSFETs
In a Si/SiGe channel p-MOSFET, a strained Si 1–x Ge x layer is epitaxially grown
a few nanometers (~2 nm) below the gate oxide (see Figure 2.14). This layer
is grown directly on a Si substrate and serves as a quantum well to confine
holes, because essentially all of the band gap difference is incorporated in
the valence band. The enhancement of hole mobility in strained SiGe layers
is, in part, due to the reduction in the hole effective mass in the transverse
direction. In addition, the compressive strain in the plane lifts the valence
band degeneracy, and the HH band dispersion becomes LH-like. Although
improvement has been achieved in SQW SiGe p-MOSFETs, at high gate bias
the Si surface layer beneath the gate oxide will also be populated by holes, and
eventually the SQW p-MOSFET will operate as a conventional Si MOSFET.
As far as short-channel effect is concerned, SiGe MOSFETs also show better performance over conventional Si devices in the deep submicron regime.
It has been shown that the velocity in 0.1 μm Si/SiGe MOSFETs is higher, and
that velocity overshoot occurs closer to the source end of the device, compared to conventional MOSFETs, to have the higher performance. Therefore,
with such promises of performance in the deep submicron regime, SiGe
devices may be regarded as an alternative to scaling. Buried channel strained
Si 1–x Ge x SQW p-MOSFETs of enhanced performance, compared to control Si
devices, have been reported. Hot-carrier degradation in device characteristics of conventional Si p-MOSFETs is caused mainly by trapped electrons in
the gate oxide or hot-carrier-induced interface traps between the gate oxide
and the surface silicon. For a SiGe device, heterointerface traps are induced
by hot carriers. Comprehensive reviews of strained layer quantum wells
(QWs) of Si 1–x Ge x and Si can be found in [1].
Strain-Engineered MOSFETs
reduction in the traverse effective mass in strained Si 1–x Ge x layers. The compressive strain in the plane also lifts the degeneracy of the valence band, and
the HH band dispersion becomes LH-like, and therefore interband scattering is reduced. Increasing the Ge percent also results in further reduction of
the effective mass. For lateral transport, it is desirable to have a light in-plane
effective mass in order to enhance the carrier mobility. In a p-MOSFET with
such structures, an intrinsic buried Si 1–x Ge x channel is desirable to reduce the
Coulomb scattering of carriers by ionised impurities. On top of this layer a thin
cap layer of Si is deposited to facilitate growing the gate oxide (see Figure 2.14).
Thermal oxidation of strained Si 1–x Ge x is not viable and results in a pile-up of
Ge at the dielectric/SiGe interface with an increase of interface state density,
thus degrading the mobility. It should be noted that one of the advantages of
buried channels is that they provide more immunity to hot-carrier degradation because carriers have to travel longer distances to reach the gate dielectric.
The transconductance reduction in buried channels is already compensated
for by the higher hole mobility in strained SiGe materials, as we explained
earlier, and also by avoiding the Si/SiO 2 interface roughness scattering.
2.8.3 Double Quantum Well p-MOSFETs
In a Si/SiGe channel p-MOSFET, a strained Si 1–x Ge x layer is epitaxially grown
a few nanometers (~2 nm) below the gate oxide (see Figure 2.14). This layer
is grown directly on a Si substrate and serves as a quantum well to confine
holes, because essentially all of the band gap difference is incorporated in
the valence band. The enhancement of hole mobility in strained SiGe layers
is, in part, due to the reduction in the hole effective mass in the transverse
direction. In addition, the compressive strain in the plane lifts the valence
band degeneracy, and the HH band dispersion becomes LH-like. Although
improvement has been achieved in SQW SiGe p-MOSFETs, at high gate bias
the Si surface layer beneath the gate oxide will also be populated by holes, and
eventually the SQW p-MOSFET will operate as a conventional Si MOSFET.
As far as short-channel effect is concerned, SiGe MOSFETs also show better performance over conventional Si devices in the deep submicron regime.
It has been shown that the velocity in 0.1 μm Si/SiGe MOSFETs is higher, and
that velocity overshoot occurs closer to the source end of the device, compared to conventional MOSFETs, to have the higher performance. Therefore,
with such promises of performance in the deep submicron regime, SiGe
devices may be regarded as an alternative to scaling. Buried channel strained
Si 1–x Ge x SQW p-MOSFETs of enhanced performance, compared to control Si
devices, have been reported. Hot-carrier degradation in device characteristics of conventional Si p-MOSFETs is caused mainly by trapped electrons in
the gate oxide or hot-carrier-induced interface traps between the gate oxide
and the surface silicon. For a SiGe device, heterointerface traps are induced
by hot carriers. Comprehensive reviews of strained layer quantum wells
(QWs) of Si 1–x Ge x and Si can be found in [1].