30
Strain-Engineered MOSFETs
use metal gate electrodes rather than conventional poly-Si gate electrodes
where high-temperature (>900°C) dopant activation is required. Metals such
as Al, W, Pt, TiN, and TaN are among the most popular metal electrodes
reported for Ge MOSFETs. The metal gate electrodes are chosen considering
their interaction with the Ge gate dielectric. The low band gap of germanium
(0.67 eV compared with 1.12 eV for Si) presents a device design challenge.
Surface channel Ge MOSFETs have been demonstrated using thin Ge oxynitride or high-k dielectric as gate insulator. Strained Ge p- and n-MOSFETs
on relaxed Si 1–x Ge x graded buffers have been reported [7]. To accommodate
the wafer incompatibility, Ge-based devices in this research are fabricated
on relaxed SiGe grown on Si wafers, and to avoid the use of GeO 2 , a thin
epitaxial Si layer is grown on top of the strained Ge channel. The Si cap
allows a high-quality interface to be formed with a conventional SiO 2 gate
and ensures basic compatibility with conventional Si CMOS processing.
For strained Ge layers on relaxed SiGe, the valence band is offset from the
relaxed virtual substrate below the channel and the Si above, resulting in a
well for holes. Furthermore, compressive strain reduces the hole effective
mass and lifts the valence band degeneracy in Ge. The smaller band gap
in Ge has been a concern because of its influence on junction leakage and
band-to-band tunneling. The junction leakage of n + /p and p + /n Ge diodes
formed by boron and phosphorus implantation can be reduced to ~10 −4 A/
cm 2 with annealing. This is considered acceptable for device operation. It has
been shown that the band-to-band tunneling can be reduced dramatically
through careful device structure design.
Monolithic integration of tensile-strained Si/germanium (Ge) channel n-MOSFET and tensile-strained Ge p-MOSFET with ultra-thin (equivalent oxide thickness ~ 14 Å) HfO 2 gate dielectric and TaN gate stack on Si substrate has been
demonstrated [8]. Defect-free Ge layer (279 nm) grown by ultra-high-vacuum
chemical vapour deposition is achieved using a two-step Ge growth technique
coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to ∼0.67% and exhibits a peak hole mobility of 250 cm 2 /V·s, which
is 100% higher than the universal Si hole mobility. The gate leakage current is
two orders of magnitude lower than the reported results on Ge bulk. A modified two-step growth of a Ge layer using an intermediate ultra-thin SiGe buffer and compliant Si epilayer occurs in an ultra-high-vacuum (UHV) chemical
vapour deposition chamber. A 279 nm thick Ge layer with a very low threading
dislocation of 6 × 10 6 cm −2 is realised on a Si substrate. We also demonstrate nand p-MOSFETs on tensile-strained Si and Ge (s-Si/s-Ge) with HfO 2 /TaN gate
stack on the Si substrate. The cross-sectional high-resolution transmission electron microscopy photograph of the Si/SiGe/Ge heterostructure in Figure 2.9(a)
shows that the dislocations are mainly confined within the SiGe buffer layer
and at the SiGe/Ge interface. The threading dislocation density of the Ge layer
above the Ge/SiGe interface is less than 10 7 /cm 2 . Surface roughness measurement using atomic force microscopy on epi-Ge shows a root mean square value
of 0.425 nm for 10 × 10 μm 2 pad. The epi-Ge thickness is about 279 nm; therefore,
Strain-Engineered MOSFETs
use metal gate electrodes rather than conventional poly-Si gate electrodes
where high-temperature (>900°C) dopant activation is required. Metals such
as Al, W, Pt, TiN, and TaN are among the most popular metal electrodes
reported for Ge MOSFETs. The metal gate electrodes are chosen considering
their interaction with the Ge gate dielectric. The low band gap of germanium
(0.67 eV compared with 1.12 eV for Si) presents a device design challenge.
Surface channel Ge MOSFETs have been demonstrated using thin Ge oxynitride or high-k dielectric as gate insulator. Strained Ge p- and n-MOSFETs
on relaxed Si 1–x Ge x graded buffers have been reported [7]. To accommodate
the wafer incompatibility, Ge-based devices in this research are fabricated
on relaxed SiGe grown on Si wafers, and to avoid the use of GeO 2 , a thin
epitaxial Si layer is grown on top of the strained Ge channel. The Si cap
allows a high-quality interface to be formed with a conventional SiO 2 gate
and ensures basic compatibility with conventional Si CMOS processing.
For strained Ge layers on relaxed SiGe, the valence band is offset from the
relaxed virtual substrate below the channel and the Si above, resulting in a
well for holes. Furthermore, compressive strain reduces the hole effective
mass and lifts the valence band degeneracy in Ge. The smaller band gap
in Ge has been a concern because of its influence on junction leakage and
band-to-band tunneling. The junction leakage of n + /p and p + /n Ge diodes
formed by boron and phosphorus implantation can be reduced to ~10 −4 A/
cm 2 with annealing. This is considered acceptable for device operation. It has
been shown that the band-to-band tunneling can be reduced dramatically
through careful device structure design.
Monolithic integration of tensile-strained Si/germanium (Ge) channel n-MOSFET and tensile-strained Ge p-MOSFET with ultra-thin (equivalent oxide thickness ~ 14 Å) HfO 2 gate dielectric and TaN gate stack on Si substrate has been
demonstrated [8]. Defect-free Ge layer (279 nm) grown by ultra-high-vacuum
chemical vapour deposition is achieved using a two-step Ge growth technique
coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to ∼0.67% and exhibits a peak hole mobility of 250 cm 2 /V·s, which
is 100% higher than the universal Si hole mobility. The gate leakage current is
two orders of magnitude lower than the reported results on Ge bulk. A modified two-step growth of a Ge layer using an intermediate ultra-thin SiGe buffer and compliant Si epilayer occurs in an ultra-high-vacuum (UHV) chemical
vapour deposition chamber. A 279 nm thick Ge layer with a very low threading
dislocation of 6 × 10 6 cm −2 is realised on a Si substrate. We also demonstrate nand p-MOSFETs on tensile-strained Si and Ge (s-Si/s-Ge) with HfO 2 /TaN gate
stack on the Si substrate. The cross-sectional high-resolution transmission electron microscopy photograph of the Si/SiGe/Ge heterostructure in Figure 2.9(a)
shows that the dislocations are mainly confined within the SiGe buffer layer
and at the SiGe/Ge interface. The threading dislocation density of the Ge layer
above the Ge/SiGe interface is less than 10 7 /cm 2 . Surface roughness measurement using atomic force microscopy on epi-Ge shows a root mean square value
of 0.425 nm for 10 × 10 μm 2 pad. The epi-Ge thickness is about 279 nm; therefore,