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Substrate-Induced Strain Engineering in CMOS Technology
Growth techniques commonly used for compressively strained Ge films
include both reduced pressure chemical vapour deposition (RPCVD) and
ultra-high-vacuum chemical vapour deposition (UHVCVD). As the first
step, low-temperature RPCVD is used to grow a fully relaxed SiGe virtual
substrate layer at 500°C with a thickness of ~135 nm, surface roughness of
0.3 nm, and Ge content of 77%. Then, low-temperature UHVCVD was used
to grow a high-quality strained pure Ge film on the SiGe virtual substrate at
300°C. Finally, a very thin strained Si layer of 1.5–2 nm thickness was grown
on the Ge layer at 550°C for the purpose of passivation and protection. The
whole epitaxial layer thickness is less than 150 nm. Due to the low growth
temperature, the two-dimensional layer-by-layer growth mode dominates
during the epitaxial process, which is a key factor for the growth of highquality strained Ge films.
2.7 Strained Ge MOSFETs
Although Ge has a low effective mass for electrons providing for higher
injection velocities, it also has a high dielectric constant and smaller band
gap, making it susceptible to higher leakage and worse short-channel effects.
One major problem for Ge CMOS device fabrication is that it is very difficult
to obtain a stable oxide gate dielectric. Poor chemical and mechanical stability prohibits the use of germanium dioxide (GeO 2 ) as a gate dielectric for Ge
devices. The water-soluble native Ge oxide that is typically present on the
upper surface of a Ge-containing material causes this gate dielectric instability. The best-known dielectric candidate for use on Ge is Ge oxynitride
(GeO x N y ). High-quality thin GeO x N y can be formed on germanium by nitridation of a thermally grown germanium oxide. Rapid thermal oxidation (RTO)
at 500–600°C followed by rapid thermal nitridation (RTN) at 600–650°C in
ammonia (NH 3 ) ambient has generally been practised. Also, high-quality
thin GeO x N y could serve as a stable interlayer for integration of novel highk dielectrics into Ge MOS devices. Recent studies on high-k dielectrics for
silicon MOSFETs by ALD and MOCVD techniques have prompted activities
to develop Ge MOSFETs implementing high-k dielectrics such as ZrO 2 and
HfO 2 (binary metal oxides). A Ge channel transistor integrated on a Si wafer
suffers from high-density defects in the Ge epilayer and poor surface roughness due to ~4.17% lattice mismatch between Si and Ge. However, one of most
challenging tasks for Ge/high-k MOS systems is the Ge surface preparation
and interface control before high-k film deposition. It appears essential to
have a surface free of germanium oxide before high-k film deposition. With
the development of high-k dielectric, Ge MOSFETs with high-k/metal gate
using different passivation methods have been successfully demonstrated
on bulk Ge wafers. Because of the low melting point of Ge, it is desirable to
Substrate-Induced Strain Engineering in CMOS Technology
Growth techniques commonly used for compressively strained Ge films
include both reduced pressure chemical vapour deposition (RPCVD) and
ultra-high-vacuum chemical vapour deposition (UHVCVD). As the first
step, low-temperature RPCVD is used to grow a fully relaxed SiGe virtual
substrate layer at 500°C with a thickness of ~135 nm, surface roughness of
0.3 nm, and Ge content of 77%. Then, low-temperature UHVCVD was used
to grow a high-quality strained pure Ge film on the SiGe virtual substrate at
300°C. Finally, a very thin strained Si layer of 1.5–2 nm thickness was grown
on the Ge layer at 550°C for the purpose of passivation and protection. The
whole epitaxial layer thickness is less than 150 nm. Due to the low growth
temperature, the two-dimensional layer-by-layer growth mode dominates
during the epitaxial process, which is a key factor for the growth of highquality strained Ge films.
2.7 Strained Ge MOSFETs
Although Ge has a low effective mass for electrons providing for higher
injection velocities, it also has a high dielectric constant and smaller band
gap, making it susceptible to higher leakage and worse short-channel effects.
One major problem for Ge CMOS device fabrication is that it is very difficult
to obtain a stable oxide gate dielectric. Poor chemical and mechanical stability prohibits the use of germanium dioxide (GeO 2 ) as a gate dielectric for Ge
devices. The water-soluble native Ge oxide that is typically present on the
upper surface of a Ge-containing material causes this gate dielectric instability. The best-known dielectric candidate for use on Ge is Ge oxynitride
(GeO x N y ). High-quality thin GeO x N y can be formed on germanium by nitridation of a thermally grown germanium oxide. Rapid thermal oxidation (RTO)
at 500–600°C followed by rapid thermal nitridation (RTN) at 600–650°C in
ammonia (NH 3 ) ambient has generally been practised. Also, high-quality
thin GeO x N y could serve as a stable interlayer for integration of novel highk dielectrics into Ge MOS devices. Recent studies on high-k dielectrics for
silicon MOSFETs by ALD and MOCVD techniques have prompted activities
to develop Ge MOSFETs implementing high-k dielectrics such as ZrO 2 and
HfO 2 (binary metal oxides). A Ge channel transistor integrated on a Si wafer
suffers from high-density defects in the Ge epilayer and poor surface roughness due to ~4.17% lattice mismatch between Si and Ge. However, one of most
challenging tasks for Ge/high-k MOS systems is the Ge surface preparation
and interface control before high-k film deposition. It appears essential to
have a surface free of germanium oxide before high-k film deposition. With
the development of high-k dielectric, Ge MOSFETs with high-k/metal gate
using different passivation methods have been successfully demonstrated
on bulk Ge wafers. Because of the low melting point of Ge, it is desirable to