26
Strain-Engineered MOSFETs
interface. As a result, a thin relaxed SiGe layer is obtained that is suitable for
deposition of a tensile Si layer. This layer can also be transferred to a new
oxidised Si wafer, which leads to a so-called strained SOI (SSOI) wafer [1].
From the viewpoint of the scaling, it is preferable that the strained Si layer
is directly formed on SiO 2 /Si substrates without utilising SiGe buffer layers. Strained silicon-on-insulator (SSOI) is a material system that combines
the carrier transport advantages of strained Si with the reduced parasitic
capacitance and improved MOSFET scalability of thin-film SOI. Also, SOI
technology provides many significant improvements (over bulk Si CMOS),
for example, in minimising parasites, decreasing leakage, improving shortchannel effects (SCEs), facilitating better noise isolation, and improving
single-event upset (SEU) tolerance. The performance benefit of combining
strained silicon with an SOI has been demonstrated in a 60 nm gate length,
n-channel MOSFET with ultra-thin thermally mixed strained silicon/
SiGe-on-insulator substrate, such as strained silicon-on-insulator (SSOI)
and SiGe-on-insulator (SGOI). Twenty to 25% drain current enhancement
has been demonstrated at short-channel length [5]. Recently, transistors
using ultra-thin strained silicon-directly-on-insulator (SSDOI) have been
demonstrated (see Figure 2.6) that eliminate the SiGe layer before transistor fabrication, thereby providing higher mobility, while eliminating the
SiGe-induced material and process integration problems.
An SSDOI structure is fabricated by a layer transfer or wafer bonding technique. First, an ultra-thin layer of strained silicon is formed epitaxially on a
relaxed silicon-germanium layer, and an oxide layer is formed on top. After
hydrogen is implanted into the SiGe layer, the wafer is flipped and bonded
to a handle substrate. A high-temperature process splits away most of the
original wafer and leaves the strained silicon and SiGe layers on top of the
oxide layer. The SiGe is then selectively removed, and transistors are fabricated on the remaining ultra-thin strained silicon. Both electron and hole
mobility enhancement have been observed in an SSDOI structure indicating that strain is retained after the complete device processing steps. Using
Strained Si
(a) Si-substrate
SiGe
Strained Si
(b) Si-substrate
Buried oxide
SiGe
Strained Si
(c) Si-substrate
Buried oxide
FIGURE 2.6
(a) Strained Si/SiGe on bulk wafer. (b) SiGe-on-insulator (SGOI) MOSFET. (c) Strained
Si-directly-on-insulator (SSDOI). (After Maiti, T. K., Process-Induced Stress Engineering in
Silicon CMOS Technology, PhD thesis, Jadavpur University, 2009.)
Strain-Engineered MOSFETs
interface. As a result, a thin relaxed SiGe layer is obtained that is suitable for
deposition of a tensile Si layer. This layer can also be transferred to a new
oxidised Si wafer, which leads to a so-called strained SOI (SSOI) wafer [1].
From the viewpoint of the scaling, it is preferable that the strained Si layer
is directly formed on SiO 2 /Si substrates without utilising SiGe buffer layers. Strained silicon-on-insulator (SSOI) is a material system that combines
the carrier transport advantages of strained Si with the reduced parasitic
capacitance and improved MOSFET scalability of thin-film SOI. Also, SOI
technology provides many significant improvements (over bulk Si CMOS),
for example, in minimising parasites, decreasing leakage, improving shortchannel effects (SCEs), facilitating better noise isolation, and improving
single-event upset (SEU) tolerance. The performance benefit of combining
strained silicon with an SOI has been demonstrated in a 60 nm gate length,
n-channel MOSFET with ultra-thin thermally mixed strained silicon/
SiGe-on-insulator substrate, such as strained silicon-on-insulator (SSOI)
and SiGe-on-insulator (SGOI). Twenty to 25% drain current enhancement
has been demonstrated at short-channel length [5]. Recently, transistors
using ultra-thin strained silicon-directly-on-insulator (SSDOI) have been
demonstrated (see Figure 2.6) that eliminate the SiGe layer before transistor fabrication, thereby providing higher mobility, while eliminating the
SiGe-induced material and process integration problems.
An SSDOI structure is fabricated by a layer transfer or wafer bonding technique. First, an ultra-thin layer of strained silicon is formed epitaxially on a
relaxed silicon-germanium layer, and an oxide layer is formed on top. After
hydrogen is implanted into the SiGe layer, the wafer is flipped and bonded
to a handle substrate. A high-temperature process splits away most of the
original wafer and leaves the strained silicon and SiGe layers on top of the
oxide layer. The SiGe is then selectively removed, and transistors are fabricated on the remaining ultra-thin strained silicon. Both electron and hole
mobility enhancement have been observed in an SSDOI structure indicating that strain is retained after the complete device processing steps. Using
Strained Si
(a) Si-substrate
SiGe
Strained Si
(b) Si-substrate
Buried oxide
SiGe
Strained Si
(c) Si-substrate
Buried oxide
FIGURE 2.6
(a) Strained Si/SiGe on bulk wafer. (b) SiGe-on-insulator (SGOI) MOSFET. (c) Strained
Si-directly-on-insulator (SSDOI). (After Maiti, T. K., Process-Induced Stress Engineering in
Silicon CMOS Technology, PhD thesis, Jadavpur University, 2009.)