27
Substrate-Induced Strain Engineering in CMOS Technology
SmartCut and wafer bonding techniques, global strain can also be integrated
on SOI substrates.
The major drawback of all global strain techniques for CMOS technology is
that they can provide only one type of strain. Since the mobilities of electrons
and holes are differently affected by different strains (compressive or tensile),
a global strain configuration, for example, compressive biaxial strain, can
be beneficial for p-MOSFETs, but deteriorate the n-MOSFET performance.
This problem is circumvented by local strain techniques, which are able to
provide different strain patterns in n- and p-MOSFETs. The development
of alternative growth techniques for the deposition of good quality Ge and
strained Si without the growth of thick relaxed SiGe buffer layers is very
important from a cost standpoint, and such techniques would hopefully
make these materials suitable for volume production.
2.6 Strained Ge Film Growth
Germanium offers higher mobility for both electrons (factor of 2) and holes
(factor of 4) than silicon. MOSFETs on Ge bulk wafer were hindered for
decades because of the lack of a stable native oxide, in contrast to its counterpart silicon. While previous Ge channel transistors were predominantly
on Ge bulk wafers, integration into Si is preferred for CMOS compatibility.
Compressive Ge provides a large enhancement to hole mobility. Ge channel
structure originally has higher hole mobility than strained Si, and the larger
hole mobility of germanium mainly comes from the smaller effective mass
of the holes. Germanium-on-insulator (GeOI) MOSFETs have become promising for monolithic 3D ICs owing to their low processing temperatures. Ge
channels are grown on Si 1–x Ge x buffer layers. Some promising results have
been obtained by the use of a dislocation blocking layer stack composed of
multiple SiGe layers. Compressive strain introduced into the Ge channel
can enhance the mobility beyond bulk Ge, since the hole effective mass is
reduced and interband phonon scattering is suppressed due to the splitting
of light-hole (LH) and heavy-hole (HH) bands. In silicon MOSFETs, biaxial
tensile strain is obtained via applying Si 1–x Ge x substrate underneath the Si
channel. Biaxial tension is not a popular stress type for germanium devices
due to the large lattice constant of germanium. Biaxial compressive stress in
the germanium MOSFET channel can be obtained by the germanium channel on top of the Si 1–x Ge x substrate.
Unstrained Ge hole mobility vs. vertical electric field and device surface
orientation is shown in Figure 2.7. Strain-enhanced hole mobility in silicon and germanium p-MOSFETs has been reported [6]. k.p calculations are
commonly used to give physical insights into hole mobility enhancement
at large stress (3 GPa for Si and 6 GPa for Ge) for stresses of technological
Substrate-Induced Strain Engineering in CMOS Technology
SmartCut and wafer bonding techniques, global strain can also be integrated
on SOI substrates.
The major drawback of all global strain techniques for CMOS technology is
that they can provide only one type of strain. Since the mobilities of electrons
and holes are differently affected by different strains (compressive or tensile),
a global strain configuration, for example, compressive biaxial strain, can
be beneficial for p-MOSFETs, but deteriorate the n-MOSFET performance.
This problem is circumvented by local strain techniques, which are able to
provide different strain patterns in n- and p-MOSFETs. The development
of alternative growth techniques for the deposition of good quality Ge and
strained Si without the growth of thick relaxed SiGe buffer layers is very
important from a cost standpoint, and such techniques would hopefully
make these materials suitable for volume production.
2.6 Strained Ge Film Growth
Germanium offers higher mobility for both electrons (factor of 2) and holes
(factor of 4) than silicon. MOSFETs on Ge bulk wafer were hindered for
decades because of the lack of a stable native oxide, in contrast to its counterpart silicon. While previous Ge channel transistors were predominantly
on Ge bulk wafers, integration into Si is preferred for CMOS compatibility.
Compressive Ge provides a large enhancement to hole mobility. Ge channel
structure originally has higher hole mobility than strained Si, and the larger
hole mobility of germanium mainly comes from the smaller effective mass
of the holes. Germanium-on-insulator (GeOI) MOSFETs have become promising for monolithic 3D ICs owing to their low processing temperatures. Ge
channels are grown on Si 1–x Ge x buffer layers. Some promising results have
been obtained by the use of a dislocation blocking layer stack composed of
multiple SiGe layers. Compressive strain introduced into the Ge channel
can enhance the mobility beyond bulk Ge, since the hole effective mass is
reduced and interband phonon scattering is suppressed due to the splitting
of light-hole (LH) and heavy-hole (HH) bands. In silicon MOSFETs, biaxial
tensile strain is obtained via applying Si 1–x Ge x substrate underneath the Si
channel. Biaxial tension is not a popular stress type for germanium devices
due to the large lattice constant of germanium. Biaxial compressive stress in
the germanium MOSFET channel can be obtained by the germanium channel on top of the Si 1–x Ge x substrate.
Unstrained Ge hole mobility vs. vertical electric field and device surface
orientation is shown in Figure 2.7. Strain-enhanced hole mobility in silicon and germanium p-MOSFETs has been reported [6]. k.p calculations are
commonly used to give physical insights into hole mobility enhancement
at large stress (3 GPa for Si and 6 GPa for Ge) for stresses of technological