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Substrate-Induced Strain Engineering in CMOS Technology
as shown in Figure 2.5. By inserting larger atoms such as Ge into the Si lattice,
the spacing between the atoms is increased, as illustrated in Figure 2.5(b).
Subsequently, a thin layer of Si atoms is laid on top of this stretched lattice,
resulting in the formation of strained Si as depicted in Figure 2.5(d). The thin
Si film would thus exhibit biaxial tensile and compressive strain in the lateral
and vertical directions, respectively. This approach is attractive for obtaining
various degrees of tensile-strained Si. However, high-misfit dislocation density arising from the abrupt transition in lattice spacing exists if the SiGe is
grown directly on the Si wafer. These dislocations could penetrate into the
surface, and the effect on device electrical performance could be detrimental.
For strained Si, a graded layer of silicon-germanium is grown on top
of a bulk silicon wafer. With the step-graded technique, one can obtain a
high-quality pure Ge final layer since the underlying buffer of low and
intermediate Ge contents acts as a filter to reduce the threading dislocations successively. A typical 2 μm thick SiGe layer having a 20–30% Ge mole
fraction, with a higher concentration of Ge atoms at the top, is used. Then
a relatively thin layer of silicon, about 20 nm thick, is deposited on top of
the Si 1–x Ge x layer. The technology for the growth of a high-quality strained
Si layer on a completely relaxed, step-graded, SiGe buffer layer has been
reviewed by several authors. Because of the lattice mismatch between Si and
Si 1–x Ge x , the lattice of the silicon layer is stretched (strained) in the plane of
the interface, resulting in enhanced carrier transport in the strained silicon
layer, which can be used as the channel of the MOSFET. Strained Si films
fabricated by the conventional method using a graded SiGe buffer layer
contain dislocations, resulting in nonuniform strain across the wafer. In the
direct Ge epitaxy, the ~4.17% lattice mismatch between Si and Ge causes two
problems, a high threading dislocation and a high surface roughness due to
island formation. The direct epitaxy technique is usually achieved with or
without surfactant mediation. In the surfactant-mediated epitaxy, a monolayer of a surfactant is first deposited. This surfactant saturates the dangling
bonds of the semiconductor surface, and consequently reduces the surface
free energy for both Ge and Si. For details, the reader may refer to the Special
Issue on Strained-Si Heterostructures and Devices [4].
2.5 Strained Si on SOI
The use of SOI substrates is another method to create virtual substrates. This
is based on oxidation of a sacrificial SiGe layer grown on a Si body. In this
case, the oxidation of SiGe layers (usually with layer thickness of 20–50 nm)
is at high temperature (1050–1150°C). Then the oxidation process favours
the Si atoms and the Ge atoms are diffused down. The buried oxide (BOX)
layer of SOI acts as a diffusion barrier leading to a condensation of Ge at the
Substrate-Induced Strain Engineering in CMOS Technology
as shown in Figure 2.5. By inserting larger atoms such as Ge into the Si lattice,
the spacing between the atoms is increased, as illustrated in Figure 2.5(b).
Subsequently, a thin layer of Si atoms is laid on top of this stretched lattice,
resulting in the formation of strained Si as depicted in Figure 2.5(d). The thin
Si film would thus exhibit biaxial tensile and compressive strain in the lateral
and vertical directions, respectively. This approach is attractive for obtaining
various degrees of tensile-strained Si. However, high-misfit dislocation density arising from the abrupt transition in lattice spacing exists if the SiGe is
grown directly on the Si wafer. These dislocations could penetrate into the
surface, and the effect on device electrical performance could be detrimental.
For strained Si, a graded layer of silicon-germanium is grown on top
of a bulk silicon wafer. With the step-graded technique, one can obtain a
high-quality pure Ge final layer since the underlying buffer of low and
intermediate Ge contents acts as a filter to reduce the threading dislocations successively. A typical 2 μm thick SiGe layer having a 20–30% Ge mole
fraction, with a higher concentration of Ge atoms at the top, is used. Then
a relatively thin layer of silicon, about 20 nm thick, is deposited on top of
the Si 1–x Ge x layer. The technology for the growth of a high-quality strained
Si layer on a completely relaxed, step-graded, SiGe buffer layer has been
reviewed by several authors. Because of the lattice mismatch between Si and
Si 1–x Ge x , the lattice of the silicon layer is stretched (strained) in the plane of
the interface, resulting in enhanced carrier transport in the strained silicon
layer, which can be used as the channel of the MOSFET. Strained Si films
fabricated by the conventional method using a graded SiGe buffer layer
contain dislocations, resulting in nonuniform strain across the wafer. In the
direct Ge epitaxy, the ~4.17% lattice mismatch between Si and Ge causes two
problems, a high threading dislocation and a high surface roughness due to
island formation. The direct epitaxy technique is usually achieved with or
without surfactant mediation. In the surfactant-mediated epitaxy, a monolayer of a surfactant is first deposited. This surfactant saturates the dangling
bonds of the semiconductor surface, and consequently reduces the surface
free energy for both Ge and Si. For details, the reader may refer to the Special
Issue on Strained-Si Heterostructures and Devices [4].
2.5 Strained Si on SOI
The use of SOI substrates is another method to create virtual substrates. This
is based on oxidation of a sacrificial SiGe layer grown on a Si body. In this
case, the oxidation of SiGe layers (usually with layer thickness of 20–50 nm)
is at high temperature (1050–1150°C). Then the oxidation process favours
the Si atoms and the Ge atoms are diffused down. The buried oxide (BOX)
layer of SOI acts as a diffusion barrier leading to a condensation of Ge at the