20
Strain-Engineered MOSFETs
with strained SiGe layers is necessary to avoid relaxation and other deteriorating effects such as Ge segregation. It is important to keep the processing
temperature around 600°C or less.
Chemical vapour deposition methods are now available for the growth
of very-high-quality strained layers. Notable among them are limited reaction processing CVD (LRPCVD), rapid thermal chemical vapour deposition
(RTCVD), and low-temperature ultra-high-vacuum chemical vapour deposition (UHVCVD). Gibbons and his group at Stanford were among the first
to demonstrate high-quality Si 1–x Ge x on Si using LRPCVD. The lamp-heated
limited reaction processing reactor (LRP) laid the groundwork for other
lamp-heated systems at Princeton University and AT&T Bell Laboratories.
The UHVCVD reactor pioneered by Meyerson and his coworkers at IBM
appeared at nearly the same time as LRPCVD. Combining a standard diffusion furnace with ultra-high vacuum, they have made a very significant impact in growing high-quality alloy layers at low temperature for
the fabrication of SiGe heterojunction bipolar transistors (HBTs). A typical
UHVCVD system includes a load lock chamber, growth chamber, precursor delivering system, and exhaust of by-product. Chambers are usually
pumped by turbo-molecular pump backup by mechanical pump. Inside the
process chamber, wafer heating is achieved by carbon susceptor. A typical UHVCVD system provides in situ plasma process capability that can
be utilised for plasma-assisted epitaxial growth or low-temperature in situ
preclean prior to the epitaxial deposition process. An excellent review of
the UHVCVD technique and of the devices fabricated using this method of
growth has been published [3].
Because Ge has an atomic spacing ~4.17% larger than that of Si, the epitaxial growth of commensurate Si 1–x Ge x on a relaxed Si substrate, below
the critical thickness, would result in a strained Si 1–x Ge x layer. The layer
of Si 1–x Ge x will then be under biaxial compressive strain in the growth
plane to match the substrate lattice atomic spacing. Figure 2.3 illustrates
the strain, misfit dislocation formation, and strain relaxation in Si 1–x Ge x
layers grown epitaxially on Si. To achieve electronic grade SiGe heteroepitaxy on Si substrate for channel application, controlling the growth
mode is important while achieving target Ge content. Ge content in SiGe
film is mainly controlled by controlling the flow rate between Si 2 H 6 and
GeH 4 . For smooth, defect-free 2D film growth, mainly growth temperature and pressure need to be tuned to suppress Stranski-Krastanov (SK)
or Volmer-Weber (VW) growth mode, which causes 3D island formation. In a UHVCVD system, reducing growth temperature for high Ge
content film in general has been beneficial to enhance 2D growth mode
and smoother surface due to reduction of surface diffusivity of adatoms.
Epitaxial deposition requires extensive efforts to develop smooth and
defect-free (less than 10 6 /cm 2 defect level) to get an optimal mobility and
minimal leakage for electronic device application.
Strain-Engineered MOSFETs
with strained SiGe layers is necessary to avoid relaxation and other deteriorating effects such as Ge segregation. It is important to keep the processing
temperature around 600°C or less.
Chemical vapour deposition methods are now available for the growth
of very-high-quality strained layers. Notable among them are limited reaction processing CVD (LRPCVD), rapid thermal chemical vapour deposition
(RTCVD), and low-temperature ultra-high-vacuum chemical vapour deposition (UHVCVD). Gibbons and his group at Stanford were among the first
to demonstrate high-quality Si 1–x Ge x on Si using LRPCVD. The lamp-heated
limited reaction processing reactor (LRP) laid the groundwork for other
lamp-heated systems at Princeton University and AT&T Bell Laboratories.
The UHVCVD reactor pioneered by Meyerson and his coworkers at IBM
appeared at nearly the same time as LRPCVD. Combining a standard diffusion furnace with ultra-high vacuum, they have made a very significant impact in growing high-quality alloy layers at low temperature for
the fabrication of SiGe heterojunction bipolar transistors (HBTs). A typical
UHVCVD system includes a load lock chamber, growth chamber, precursor delivering system, and exhaust of by-product. Chambers are usually
pumped by turbo-molecular pump backup by mechanical pump. Inside the
process chamber, wafer heating is achieved by carbon susceptor. A typical UHVCVD system provides in situ plasma process capability that can
be utilised for plasma-assisted epitaxial growth or low-temperature in situ
preclean prior to the epitaxial deposition process. An excellent review of
the UHVCVD technique and of the devices fabricated using this method of
growth has been published [3].
Because Ge has an atomic spacing ~4.17% larger than that of Si, the epitaxial growth of commensurate Si 1–x Ge x on a relaxed Si substrate, below
the critical thickness, would result in a strained Si 1–x Ge x layer. The layer
of Si 1–x Ge x will then be under biaxial compressive strain in the growth
plane to match the substrate lattice atomic spacing. Figure 2.3 illustrates
the strain, misfit dislocation formation, and strain relaxation in Si 1–x Ge x
layers grown epitaxially on Si. To achieve electronic grade SiGe heteroepitaxy on Si substrate for channel application, controlling the growth
mode is important while achieving target Ge content. Ge content in SiGe
film is mainly controlled by controlling the flow rate between Si 2 H 6 and
GeH 4 . For smooth, defect-free 2D film growth, mainly growth temperature and pressure need to be tuned to suppress Stranski-Krastanov (SK)
or Volmer-Weber (VW) growth mode, which causes 3D island formation. In a UHVCVD system, reducing growth temperature for high Ge
content film in general has been beneficial to enhance 2D growth mode
and smoother surface due to reduction of surface diffusivity of adatoms.
Epitaxial deposition requires extensive efforts to develop smooth and
defect-free (less than 10 6 /cm 2 defect level) to get an optimal mobility and
minimal leakage for electronic device application.