16
Strain-Engineered MOSFETs
In this chapter, we focus first on the strain-engineered substrates and
the principles of strain engineering in Si. Electronic properties of strainengineered substrates will be covered in Chapter 4. The strain in a Si and
SiGe system, a composition of Si with Ge (or C), can provide strain that
affects the electrical and optical properties of Si. Strain can be generated
from lattice-mismatched film growth in epitaxial heterostructures, intrinsic
stress in deposited thin films, and applied external stress. Although many
strain technologies have been developed and introduced, they are divided
into two distinct categories: global techniques where strain is introduced
into the whole wafer and local techniques where stress is delivered to each
transistor separately and independently. Local stress is usually introduced
during MOSFET fabrication and is also known as process-induced stress,
which will be covered in Chapter 3. In this chapter, we also review the
major integration challenges and mobility enhancement associated with
Ge surface channel devices as well as strained Ge buried channel devices.
The smaller band gap (0.67 vs. 1.12 eV for Si) and the much lower melting
point (934°C vs. 1400°C for Si) present additional processing challenges for
integrating Ge channel MOSFETs. Replacing the channel material is a very
significant change from a manufacturing standpoint, and such a modification has not always been successful in volume production for conventional
Si CMOS technology. We shall focus on the evaluation of some of the technological alternatives for the integration of channel materials, such as SiGe,
Ge, and strained Si in a MOSFET.
2.1 Substrate Engineering
There has been remarkable progress in recent years in Si/SiGe technology. Many novel and advanced devices with high performance have been
reported using a SiGe material system [1]. Si and Ge are completely miscible over the entire compositional range and give rise to alloys with a diamond crystal structure. The lattice mismatch between Si and Ge is ~4.17%
at room temperature. The lattice constant of Si 1–x Ge x alloys varies linearly,
obeying Vegard’s rule. When a SiGe alloy layer is deposited on a thick Si
substrate, the mismatch is accommodated in either of two ways: tetragonal
distortion of the lattice and generation of misfit dislocations at the interface give rise to relaxed or unstrained growth. Initially an epitaxial film
of Si 1–x Ge x grown on Si is pseudomorphic; that is, it has the in-plane lattice constant of Si and is compressively strained. However, once the critical
thickness for pseudomorphic growth is exceeded, strain is relieved by the
formation of dislocations.
One of the most difficult and continuing research challenges in the
semiconductor industry is the ability to grow high-quality films using
Strain-Engineered MOSFETs
In this chapter, we focus first on the strain-engineered substrates and
the principles of strain engineering in Si. Electronic properties of strainengineered substrates will be covered in Chapter 4. The strain in a Si and
SiGe system, a composition of Si with Ge (or C), can provide strain that
affects the electrical and optical properties of Si. Strain can be generated
from lattice-mismatched film growth in epitaxial heterostructures, intrinsic
stress in deposited thin films, and applied external stress. Although many
strain technologies have been developed and introduced, they are divided
into two distinct categories: global techniques where strain is introduced
into the whole wafer and local techniques where stress is delivered to each
transistor separately and independently. Local stress is usually introduced
during MOSFET fabrication and is also known as process-induced stress,
which will be covered in Chapter 3. In this chapter, we also review the
major integration challenges and mobility enhancement associated with
Ge surface channel devices as well as strained Ge buried channel devices.
The smaller band gap (0.67 vs. 1.12 eV for Si) and the much lower melting
point (934°C vs. 1400°C for Si) present additional processing challenges for
integrating Ge channel MOSFETs. Replacing the channel material is a very
significant change from a manufacturing standpoint, and such a modification has not always been successful in volume production for conventional
Si CMOS technology. We shall focus on the evaluation of some of the technological alternatives for the integration of channel materials, such as SiGe,
Ge, and strained Si in a MOSFET.
2.1 Substrate Engineering
There has been remarkable progress in recent years in Si/SiGe technology. Many novel and advanced devices with high performance have been
reported using a SiGe material system [1]. Si and Ge are completely miscible over the entire compositional range and give rise to alloys with a diamond crystal structure. The lattice mismatch between Si and Ge is ~4.17%
at room temperature. The lattice constant of Si 1–x Ge x alloys varies linearly,
obeying Vegard’s rule. When a SiGe alloy layer is deposited on a thick Si
substrate, the mismatch is accommodated in either of two ways: tetragonal
distortion of the lattice and generation of misfit dislocations at the interface give rise to relaxed or unstrained growth. Initially an epitaxial film
of Si 1–x Ge x grown on Si is pseudomorphic; that is, it has the in-plane lattice constant of Si and is compressively strained. However, once the critical
thickness for pseudomorphic growth is exceeded, strain is relieved by the
formation of dislocations.
One of the most difficult and continuing research challenges in the
semiconductor industry is the ability to grow high-quality films using