15
2
Substrate-Induced Strain Engineering
in CMOS Technology
As the conventional metal-oxide-semiconductor field-effect transistor
(MOSFET) scaling reached its fundamental limits, several novel techniques
have been investigated to extend the CMOS road map. One of these techniques is the introduction of strain in the silicon channel of a MOSFET to
obtain higher mobility. Enhancement in mobility may also be obtained by
choosing the substrate surface orientation. The major mobility enhancement technologies currently in use can be grouped in two main categories:
substrate induced and process induced. Application of strain results in two
effects: shift in the band energy and degeneracy splitting of electronic states.
Electron mobility is increased by the degeneracy splitting of the conduction
band minimum, so the speed of devices fabricated on strained Si is enhanced.
One of the predecessors of process-induced strained Si to enhance MOSFET
performance is the research that showed enhanced electron mobilities in
n-type (100) Si/Si 1–x Ge x multilayer heterostructures and hole mobilities in
p-type (100) Si/i-Si 1–x Ge x /Si double heterostructures in early 1980s [1].
The substrate-induced strain techniques use the advantage of either a builtup strain or preferential crystal orientations of the wafer at the process start.
Strained Si is one of the key technology boosters identified by the International
Technology Roadmap for Semiconductors (ITRS) as being essential to the
continuation of classical scaling. The enhanced carrier mobilities made possible through strain engineering result in device performance improvements.
However, biaxial stress technology was not adopted in Si CMOS technology due to various issues, which include defects in the substrate, process
complexity, cost, and performance loss at high vertical electric fields. Also,
strained Si substrates are not yet commercially available with tolerable defect
densities. Biaxial strain has also the disadvantage of near-zero hole mobility
enhancement at high vertical field, while uniaxial stress shows hole mobility enhancement at large vertical electric fields. Another way of enhancing
channel mobility without the introduction of any new channel materials is
the use of hybrid crystal orientation of Si substrates. A two to three times
boost in hole mobility and about 40–60% improvement in I on /I off performance
for p-MOSFET devices is possible by merely changing the starting crystal
surface to a (110) Si instead of the typically used (100) Si. Various processing
techniques have been proposed to utilise the (100) Si for n-MOSFET and (110)
Si for p-MOSFET devices in a silicon-on-insulator (SOI) configuration.
2
Substrate-Induced Strain Engineering
in CMOS Technology
As the conventional metal-oxide-semiconductor field-effect transistor
(MOSFET) scaling reached its fundamental limits, several novel techniques
have been investigated to extend the CMOS road map. One of these techniques is the introduction of strain in the silicon channel of a MOSFET to
obtain higher mobility. Enhancement in mobility may also be obtained by
choosing the substrate surface orientation. The major mobility enhancement technologies currently in use can be grouped in two main categories:
substrate induced and process induced. Application of strain results in two
effects: shift in the band energy and degeneracy splitting of electronic states.
Electron mobility is increased by the degeneracy splitting of the conduction
band minimum, so the speed of devices fabricated on strained Si is enhanced.
One of the predecessors of process-induced strained Si to enhance MOSFET
performance is the research that showed enhanced electron mobilities in
n-type (100) Si/Si 1–x Ge x multilayer heterostructures and hole mobilities in
p-type (100) Si/i-Si 1–x Ge x /Si double heterostructures in early 1980s [1].
The substrate-induced strain techniques use the advantage of either a builtup strain or preferential crystal orientations of the wafer at the process start.
Strained Si is one of the key technology boosters identified by the International
Technology Roadmap for Semiconductors (ITRS) as being essential to the
continuation of classical scaling. The enhanced carrier mobilities made possible through strain engineering result in device performance improvements.
However, biaxial stress technology was not adopted in Si CMOS technology due to various issues, which include defects in the substrate, process
complexity, cost, and performance loss at high vertical electric fields. Also,
strained Si substrates are not yet commercially available with tolerable defect
densities. Biaxial strain has also the disadvantage of near-zero hole mobility
enhancement at high vertical field, while uniaxial stress shows hole mobility enhancement at large vertical electric fields. Another way of enhancing
channel mobility without the introduction of any new channel materials is
the use of hybrid crystal orientation of Si substrates. A two to three times
boost in hole mobility and about 40–60% improvement in I on /I off performance
for p-MOSFET devices is possible by merely changing the starting crystal
surface to a (110) Si instead of the typically used (100) Si. Various processing
techniques have been proposed to utilise the (100) Si for n-MOSFET and (110)
Si for p-MOSFET devices in a silicon-on-insulator (SOI) configuration.