17
Substrate-Induced Strain Engineering in CMOS Technology
lattice-mismatched materials known as heteroepitaxy. The germaniumsilicon system has been extensively studied because of the many potential
applications of Ge and advantages over Si. Below a critical thickness, the
lattice mismatch between Ge and Si causes the grown film to match the
lattice constant of the underlying Si substrate, and hence strain the layer.
However, above a critical thickness, it is energetically favourable for the
layer to create dislocations to relieve this strain. In addition, due to the
lattice mismatch associated with the system, an alternative mechanism of
strain relaxation, islanding, often leads to rough surfaces. We describe the
main challenges of the SiGe heteroepitaxial system. Different strained and
relaxed buffer layers (RBLs) of Si 1–x Ge x (x = 0.13 to 1.00) epitaxially grown
on (001) Si substrates are discussed. The main techniques currently used
to introduce strain are shown in Figure 2.1. This group includes a wide
variety of different wafer types and materials. The wafers can be bulk
wafers or SOI based. For p-MOSFETs, mainly compressively strained SiGe
layers are used. Ge contents between 20 and 30% and layer thicknesses on
the order of 10 nm are required. This provides a stress level in the range
1.5–2 GPa. To achieve tensile strain, virtual substrates (VSs) are normally
used. In this case a relaxed SiGe or Ge layer is required on top of a Si
wafer. A subsequent deposition of a Si or SiGe layer creates a strained top
layer. The strain in the top layer can be tensile or compressive depending
Substrate-based
Biaxial
Strain
Bulk
SOI
Relaxed
SiGe
Strained
SiGe
Tensile/
Compressive
Compressive
Tensile/
Compressive
Tensile
SGOI
sSOI
In Plane
Device
Rotation
Hot
nMOS
and
pMOS
Crystallographic
Rotation
Crystal
Orientation
Natural mobility boost
FIGURE 2.1
Different substrate-based mobility enhancement technologies. (After Hallstedt, J., Epitaxy and
Characterization of SiGe:C Layers Grown by Reduced Pressure Chemical Vapor Deposition,
PhD thesis, Royal Institute of Technology (KTH), Sweden, 2004.)
Substrate-Induced Strain Engineering in CMOS Technology
lattice-mismatched materials known as heteroepitaxy. The germaniumsilicon system has been extensively studied because of the many potential
applications of Ge and advantages over Si. Below a critical thickness, the
lattice mismatch between Ge and Si causes the grown film to match the
lattice constant of the underlying Si substrate, and hence strain the layer.
However, above a critical thickness, it is energetically favourable for the
layer to create dislocations to relieve this strain. In addition, due to the
lattice mismatch associated with the system, an alternative mechanism of
strain relaxation, islanding, often leads to rough surfaces. We describe the
main challenges of the SiGe heteroepitaxial system. Different strained and
relaxed buffer layers (RBLs) of Si 1–x Ge x (x = 0.13 to 1.00) epitaxially grown
on (001) Si substrates are discussed. The main techniques currently used
to introduce strain are shown in Figure 2.1. This group includes a wide
variety of different wafer types and materials. The wafers can be bulk
wafers or SOI based. For p-MOSFETs, mainly compressively strained SiGe
layers are used. Ge contents between 20 and 30% and layer thicknesses on
the order of 10 nm are required. This provides a stress level in the range
1.5–2 GPa. To achieve tensile strain, virtual substrates (VSs) are normally
used. In this case a relaxed SiGe or Ge layer is required on top of a Si
wafer. A subsequent deposition of a Si or SiGe layer creates a strained top
layer. The strain in the top layer can be tensile or compressive depending
Substrate-based
Biaxial
Strain
Bulk
SOI
Relaxed
SiGe
Strained
SiGe
Tensile/
Compressive
Compressive
Tensile/
Compressive
Tensile
SGOI
sSOI
In Plane
Device
Rotation
Hot
nMOS
and
pMOS
Crystallographic
Rotation
Crystal
Orientation
Natural mobility boost
FIGURE 2.1
Different substrate-based mobility enhancement technologies. (After Hallstedt, J., Epitaxy and
Characterization of SiGe:C Layers Grown by Reduced Pressure Chemical Vapor Deposition,
PhD thesis, Royal Institute of Technology (KTH), Sweden, 2004.)