12
Strain-Engineered MOSFETs
the design process. Handling device variability during design process will
require accurate models of variability and its dependence on designable
parameters. In order to continue scaling, there is also a need to reduce margins in the design by classifying process variations as systematic or random.
Chapter 10 provides an overview of current practises as well as nearfuture research needs in developing a SPICE model for process, variability characterisation, and a process compact model. We present a TCAD
methodology of strain-engineered MOSFETs providing the data flow from
process simulation to comprehensive and systematic process variability
simulation via device simulation, and process compact model analyses to
improve design for manufacturing and parametric yield. Basic processrelated simulations have been performed using the Sentaurus Process tool
to understand the type of stress, device structure, halo implant, gate oxidation, source/drain implant, and annealing temperature. This information
is then carried forward to the Sentaurus Device simulation and modelling tool, which provides the electrical characteristics of device structures
generated via process simulation. The outputs of the process and device
simulations are fed in the process compact modelling framework, i.e.,
Paramos. Compact SPICE models as a function of process parameter variations are then extracted. The model parameters have been calibrated with
the extracted SPICE parameters from TCAD simulations. The usefulness of
the process compact model for process optimisation as an overall design
for manufacturing solution is shown.
1.11 Summary
Beyond the 22 nm technology node, replacing Si channel with other materials having a higher intrinsic mobility has been proposed. Candidates like
Ge and III-V compound semiconductors, e.g., GaAs, are currently being
investigated. However, adopting these materials for device fabrication has
problems of its own. Special attention should be given to the analysis of
performance boosting high-k/metal gate and stress engineering technologies and how they can be used to leverage either speed or leakage or both.
New processes in terms of integration of the new substrates based on either
a hybrid orientation technique or direct Ge or III-V semiconductors need
to be developed. The ultimate scaled MOSFET will be multigate, possibly
with advanced and enhanced transport innovations such as III-V channels
and nanowire MOSFETs. Finding a compatible gate dielectric, source/drain
contact and other integration issues will have to be overcome before they
can be used in manufacturing. Compatibility of different mobility enhancement technologies needs to be researched to boost device performance.
Challenges for back-end processes include the search for new materials to
Strain-Engineered MOSFETs
the design process. Handling device variability during design process will
require accurate models of variability and its dependence on designable
parameters. In order to continue scaling, there is also a need to reduce margins in the design by classifying process variations as systematic or random.
Chapter 10 provides an overview of current practises as well as nearfuture research needs in developing a SPICE model for process, variability characterisation, and a process compact model. We present a TCAD
methodology of strain-engineered MOSFETs providing the data flow from
process simulation to comprehensive and systematic process variability
simulation via device simulation, and process compact model analyses to
improve design for manufacturing and parametric yield. Basic processrelated simulations have been performed using the Sentaurus Process tool
to understand the type of stress, device structure, halo implant, gate oxidation, source/drain implant, and annealing temperature. This information
is then carried forward to the Sentaurus Device simulation and modelling tool, which provides the electrical characteristics of device structures
generated via process simulation. The outputs of the process and device
simulations are fed in the process compact modelling framework, i.e.,
Paramos. Compact SPICE models as a function of process parameter variations are then extracted. The model parameters have been calibrated with
the extracted SPICE parameters from TCAD simulations. The usefulness of
the process compact model for process optimisation as an overall design
for manufacturing solution is shown.
1.11 Summary
Beyond the 22 nm technology node, replacing Si channel with other materials having a higher intrinsic mobility has been proposed. Candidates like
Ge and III-V compound semiconductors, e.g., GaAs, are currently being
investigated. However, adopting these materials for device fabrication has
problems of its own. Special attention should be given to the analysis of
performance boosting high-k/metal gate and stress engineering technologies and how they can be used to leverage either speed or leakage or both.
New processes in terms of integration of the new substrates based on either
a hybrid orientation technique or direct Ge or III-V semiconductors need
to be developed. The ultimate scaled MOSFET will be multigate, possibly
with advanced and enhanced transport innovations such as III-V channels
and nanowire MOSFETs. Finding a compatible gate dielectric, source/drain
contact and other integration issues will have to be overcome before they
can be used in manufacturing. Compatibility of different mobility enhancement technologies needs to be researched to boost device performance.
Challenges for back-end processes include the search for new materials to