13
Introduction
meet high conductivity and low dielectric permittivity, and interconnect
reliability, electromigration, and interaction with assembly and packaging
for 3D structures. With the usage of stacked chips and through-silicon vias,
stress, thermal, and electrical performance co-analyses will be increasingly
needed.
Additional Reading
1. C. K. Maiti, S. Chattopadhyay, and L. K. Bera, Strained-Si Heterostructure Field
Effect Devices, CRC Press, Boca Raton, FL, 2007.
2. G. A. Armstrong and C. K. Maiti, Technology Computer Aided Design for Si, SiGe
and GaAs Integrated Circuits, IET, London, UK, 2008.
3. V. Sverdlov, Strain-Induced Effects in Advanced MOSFETs, Springer-Verlag, Wien,
Austria, 2011.
4. C. Claeys and E. Simoen, Germanium-Based Technologies: From Materials to Devices,
Elsevier, Amsterdam, 2007.
5. Y. Sun, S. E. Thompson, and T. Nishida, Strain Effect in Semiconductors Theory and
Device Applications, Springer Science + Business Media, LLC, New York, USA,
2010.
6. C. C. Chiang and J. Kawa, Design for Manufacturability and Yield for Nano-Scale
CMOS, Springer, Dordrecht, Netherlands, 2007.
7. J.-P. Colinge, Ed., FinFETs and Other Multi-Gate Transistors, Springer Science +
Business Media, LLC, New York, USA, 2008.
8. Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer
Science + Business Media, LLC, New York, USA, 2011.