10
Strain-Engineered MOSFETs
necessitate costly redesign cycles. Technology computer-aided design is an
indispensable tool for development and optimisation of new generations
of electronic devices in industrial environments. Chapter 7 is dedicated to
the technology CAD modelling of strain-engineered MOSFETs in processinduced strain technologies.
1.8 Reliability of Strain-Engineered MOSFETs
Scaling the conventional MOSFETs has so far been more or less a straightforward process. But the physical limitations encountered beyond the 130 nm
node brought the necessity of exploration of new gate stack high-k materials, mobility enhancers, and even new device architectures. The new technologies come along with many advantages, but also raise many concerns
about their reliability. Systematic studies to determine the key parameters
controlling the reliability are necessary. It is important to identify the intrinsic reliability problems of the advanced devices, to distinguish them from
extrinsic effects of processing, and to suggest new methods for reliability
improvement. In Chapter 8, the bias temperature instabilities (BTIs) of some
of the new generation devices, such as high-k/metal gate (HK-MG) stacks,
strain-engineered devices with enhanced mobility, and FinFET devices, are
considered. Technology CAD has been used to study the effects of strain
on the negative bias temperature instabilities (NBTIs) in process-induced
strained Si p-MOSFETs and hot-carrier injection in process-induced strained
Si n-MOSFETs.
1.9 Process Compact Modelling
Aggressive technology scaling has led to large uncertainties in device and
interconnect characteristics for deep-submicron circuits. Many physical phenomena, unforeseen in the larger dimensions, such as short-channel effect
(SCE) and exponential increase in leakage, are becoming the major bottlenecks for continuous technology scaling. Increasing variations (both interdie and intradie) in device parameters (channel length, gate width, oxide
thickness, device threshold voltage, etc.) produce a large spread in the delay
and power consumption in advanced integrated circuits. The presence of
large process variations and deep-submicron effects requires a paradigm
change in the design and optimisation of large-scale circuits and systems.
Innovations only in the area of technology/circuit design are not enough
to combat against the different shortcomings of the process variations.
Strain-Engineered MOSFETs
necessitate costly redesign cycles. Technology computer-aided design is an
indispensable tool for development and optimisation of new generations
of electronic devices in industrial environments. Chapter 7 is dedicated to
the technology CAD modelling of strain-engineered MOSFETs in processinduced strain technologies.
1.8 Reliability of Strain-Engineered MOSFETs
Scaling the conventional MOSFETs has so far been more or less a straightforward process. But the physical limitations encountered beyond the 130 nm
node brought the necessity of exploration of new gate stack high-k materials, mobility enhancers, and even new device architectures. The new technologies come along with many advantages, but also raise many concerns
about their reliability. Systematic studies to determine the key parameters
controlling the reliability are necessary. It is important to identify the intrinsic reliability problems of the advanced devices, to distinguish them from
extrinsic effects of processing, and to suggest new methods for reliability
improvement. In Chapter 8, the bias temperature instabilities (BTIs) of some
of the new generation devices, such as high-k/metal gate (HK-MG) stacks,
strain-engineered devices with enhanced mobility, and FinFET devices, are
considered. Technology CAD has been used to study the effects of strain
on the negative bias temperature instabilities (NBTIs) in process-induced
strained Si p-MOSFETs and hot-carrier injection in process-induced strained
Si n-MOSFETs.
1.9 Process Compact Modelling
Aggressive technology scaling has led to large uncertainties in device and
interconnect characteristics for deep-submicron circuits. Many physical phenomena, unforeseen in the larger dimensions, such as short-channel effect
(SCE) and exponential increase in leakage, are becoming the major bottlenecks for continuous technology scaling. Increasing variations (both interdie and intradie) in device parameters (channel length, gate width, oxide
thickness, device threshold voltage, etc.) produce a large spread in the delay
and power consumption in advanced integrated circuits. The presence of
large process variations and deep-submicron effects requires a paradigm
change in the design and optimisation of large-scale circuits and systems.
Innovations only in the area of technology/circuit design are not enough
to combat against the different shortcomings of the process variations.