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Strain-Engineered MOSFETs
device scaling. At high vertical electric fields, biaxial tensile strain enhances
electron mobility, while uniaxial compressive strain enhances hole mobility.
With the extreme scaling down of MOSFETs in high-volume manufacturing, it is imperative to develop technology computer-aided design
(TCAD)-based methodology encompassing process design to device simulation, characterisation for SPICE parameter extraction, and optimisation
of design for manufacturing to increase yield. A methodology for capturing process variability in SPICE models has been discussed. The model
was validated by comparing device characteristics from the extracted
SPICE parameters with those obtained from TCAD simulations. Variationaware analogue and mixed-signal circuit design will require advanced
models for process variations. We have focused on the process variation of strain-engineered MOSFETs at the device level, but circuit- and
architecture-level approaches should be investigated to further mitigate
process variations. The optimisation has been employed only on MOSFET
design parameters, such as oxide thickness, gate length, channel doping
concentration, etc. However, tape-out optimisation by modern lithography technologies is required. Furthermore, optimisation of all hierarchy
levels (device, circuit, gate, and architecture) is required to suppress the
process variation effects, reduce the power consumption, and improve the
device performance.
We have discussed through-silicon via (TSV) modelling for simple structures. Optimisation of the size and placement of ground plugs to maximise
noise isolation and to minimise area penalty is necessary. A comprehensive
understanding of TSV stress-induced variation is also needed. Development
of new techniques in mitigating TSV-induced substrate noise and their characterisation is also necessary. Toward understanding of reliability issues,
negative bias temperature instability (NBTI) and hot-carrier injection (HCI)
degradation in strain-engineered MOSFETs has been considered. The models used to study degradation mechanisms should further be modified for
ultra-short-channel devices. Toward better understanding of the degradation mechanisms, such as circuit-level degradation, the combined effects of
NBTI and HCI need to be considered. However, there will be an ultimate
limit for the scaling when ballistic transport will take place. It is not clear if
strain techniques will still be useful at that stage. Last, an integrated effort is
necessary to work on novel CMOS structures involving (1) growth and fabrication of novel substrate materials, (2) device/circuit fabrication, (3) characterisation, and (4) modelling.
Strain-Engineered MOSFETs
device scaling. At high vertical electric fields, biaxial tensile strain enhances
electron mobility, while uniaxial compressive strain enhances hole mobility.
With the extreme scaling down of MOSFETs in high-volume manufacturing, it is imperative to develop technology computer-aided design
(TCAD)-based methodology encompassing process design to device simulation, characterisation for SPICE parameter extraction, and optimisation
of design for manufacturing to increase yield. A methodology for capturing process variability in SPICE models has been discussed. The model
was validated by comparing device characteristics from the extracted
SPICE parameters with those obtained from TCAD simulations. Variationaware analogue and mixed-signal circuit design will require advanced
models for process variations. We have focused on the process variation of strain-engineered MOSFETs at the device level, but circuit- and
architecture-level approaches should be investigated to further mitigate
process variations. The optimisation has been employed only on MOSFET
design parameters, such as oxide thickness, gate length, channel doping
concentration, etc. However, tape-out optimisation by modern lithography technologies is required. Furthermore, optimisation of all hierarchy
levels (device, circuit, gate, and architecture) is required to suppress the
process variation effects, reduce the power consumption, and improve the
device performance.
We have discussed through-silicon via (TSV) modelling for simple structures. Optimisation of the size and placement of ground plugs to maximise
noise isolation and to minimise area penalty is necessary. A comprehensive
understanding of TSV stress-induced variation is also needed. Development
of new techniques in mitigating TSV-induced substrate noise and their characterisation is also necessary. Toward understanding of reliability issues,
negative bias temperature instability (NBTI) and hot-carrier injection (HCI)
degradation in strain-engineered MOSFETs has been considered. The models used to study degradation mechanisms should further be modified for
ultra-short-channel devices. Toward better understanding of the degradation mechanisms, such as circuit-level degradation, the combined effects of
NBTI and HCI need to be considered. However, there will be an ultimate
limit for the scaling when ballistic transport will take place. It is not clear if
strain techniques will still be useful at that stage. Last, an integrated effort is
necessary to work on novel CMOS structures involving (1) growth and fabrication of novel substrate materials, (2) device/circuit fabrication, (3) characterisation, and (4) modelling.