287
11
Conclusions
Strain engineering continues to evolve and will remain one of the key
performance enablers for future generations of complementary metaloxide-semiconductor (CMOS) technologies. In this monograph we have
attempted to give some insight into process design, device modelling
and simulation, and optimisation of strain-engineered metal-oxidesemiconductor field-effect transistors (MOSFETs). We have discussed
the challenges involved in the heterogeneous integration of novel bandengineered materials and strained quantum wells on a Si platform. We
have provided an overview of the major strain engineering techniques
that have remarkably advanced the silicon CMOS transistor architecture, including embedded SiGe (e-SiGe), embedded SiC (e-SiC), the stress
memorisation technique (SMT), dual-stress liners (DSLs), and the stress
proximity technique (SPT). The application of local strain, however, is
limited for further scaling beyond 22 nm, and as such, new methods
of strain generation in the transistor channel region will be required.
One possible option could be the combination of global and local strain.
Multigate devices employing high-k gate dielectrics have emerged as a
promising solution overcoming the scaling limitations of planar bulk
CMOS. The advent of high-k/metal gate has brought additional strain
benefits. Current techniques for generating strain in silicon are limited
to a single type of strain (uniaxial or biaxial) within the substrate, which
is clearly not optimum for simultaneous enhancement of hole and electron mobilities. Development of a new technology to generate biaxial and
uniaxial silicon strain side by side on a single silicon-on-insulator (SOI)
wafer will be of great technological importance.
Power dissipation is becoming a limiting factor in high-performance
system design as technology scales and device integration level increases.
Reduction in system power is not only important to improve battery life in
portable devices, but it also plays an important role in enhancing the system reliability. Supply voltage scaling is emerging as an effective technique
for reducing both dynamic and leakage power. Possible future innovations
in device structures, novel process modules, and material systems have the
potential to successfully address upcoming scaling challenges in a powerlimited era. The convergence of new transistor structures and materials will
be critical for successfully scaling CMOS transistors through the next decade.
Strained Si is of technological interest for its ability to increase carrier mobilities in MOSFETs, and thereby improve circuit performance without requiring
11
Conclusions
Strain engineering continues to evolve and will remain one of the key
performance enablers for future generations of complementary metaloxide-semiconductor (CMOS) technologies. In this monograph we have
attempted to give some insight into process design, device modelling
and simulation, and optimisation of strain-engineered metal-oxidesemiconductor field-effect transistors (MOSFETs). We have discussed
the challenges involved in the heterogeneous integration of novel bandengineered materials and strained quantum wells on a Si platform. We
have provided an overview of the major strain engineering techniques
that have remarkably advanced the silicon CMOS transistor architecture, including embedded SiGe (e-SiGe), embedded SiC (e-SiC), the stress
memorisation technique (SMT), dual-stress liners (DSLs), and the stress
proximity technique (SPT). The application of local strain, however, is
limited for further scaling beyond 22 nm, and as such, new methods
of strain generation in the transistor channel region will be required.
One possible option could be the combination of global and local strain.
Multigate devices employing high-k gate dielectrics have emerged as a
promising solution overcoming the scaling limitations of planar bulk
CMOS. The advent of high-k/metal gate has brought additional strain
benefits. Current techniques for generating strain in silicon are limited
to a single type of strain (uniaxial or biaxial) within the substrate, which
is clearly not optimum for simultaneous enhancement of hole and electron mobilities. Development of a new technology to generate biaxial and
uniaxial silicon strain side by side on a single silicon-on-insulator (SOI)
wafer will be of great technological importance.
Power dissipation is becoming a limiting factor in high-performance
system design as technology scales and device integration level increases.
Reduction in system power is not only important to improve battery life in
portable devices, but it also plays an important role in enhancing the system reliability. Supply voltage scaling is emerging as an effective technique
for reducing both dynamic and leakage power. Possible future innovations
in device structures, novel process modules, and material systems have the
potential to successfully address upcoming scaling challenges in a powerlimited era. The convergence of new transistor structures and materials will
be critical for successfully scaling CMOS transistors through the next decade.
Strained Si is of technological interest for its ability to increase carrier mobilities in MOSFETs, and thereby improve circuit performance without requiring