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Strain-Engineered MOSFETs
References
1. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De,
Parameter Variations and Impacts on Circuits and Microarchitecture, Proc.
Design Automation Conference, 338–342, 2003.
2. Semiconductor Industry Association, International Technology Roadmap for
Semiconductors (ITRS), 2009, http://public. itrs.net.
3. C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F.
Leverd, P. Stolk, F. Boeuf, and F. Arnaud, Stress Memorization Technique (SMT)
Optimization for 45 nm CMOS, Proc. VLSI Tech. Dig., 78–79, 2006.
4. J. Jaffari and M. Anis, Variability-Aware Device Optimization under i ON
and Leakage Current Constraints, Proceedings of International Symposium
on Low Power Electronics and Design (ISLPED 06), Tegernsee, Germany,
October 2006.
5. C. C. Chiang and J. Kawa, Design for Manufacturability and Yield for Nano-Scale
CMOS, Springer, Dordrecht, 2007.
6. M. Orshansky, S. R. Nassif, and D. Boning, Design for Manufacturability and
Statistical Design: A Constructive Approach, Springer Science + Business Media,
LLC, New York, USA, 2008.
7. A. Inselberg, The Plane with Parallel Coordinates, Visual Computer, 1, 69–91, 1985.
8. T. K. Maiti and C. K. Maiti, Strained-Engineered MOSFETs: Design and
Optimization Using TCAD, Proceedings of International SiGe Technology and
Device Meeting (ISTDM), Taiwan, Mon-P1-60, 2008.
Strain-Engineered MOSFETs
References
1. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De,
Parameter Variations and Impacts on Circuits and Microarchitecture, Proc.
Design Automation Conference, 338–342, 2003.
2. Semiconductor Industry Association, International Technology Roadmap for
Semiconductors (ITRS), 2009, http://public. itrs.net.
3. C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F.
Leverd, P. Stolk, F. Boeuf, and F. Arnaud, Stress Memorization Technique (SMT)
Optimization for 45 nm CMOS, Proc. VLSI Tech. Dig., 78–79, 2006.
4. J. Jaffari and M. Anis, Variability-Aware Device Optimization under i ON
and Leakage Current Constraints, Proceedings of International Symposium
on Low Power Electronics and Design (ISLPED 06), Tegernsee, Germany,
October 2006.
5. C. C. Chiang and J. Kawa, Design for Manufacturability and Yield for Nano-Scale
CMOS, Springer, Dordrecht, 2007.
6. M. Orshansky, S. R. Nassif, and D. Boning, Design for Manufacturability and
Statistical Design: A Constructive Approach, Springer Science + Business Media,
LLC, New York, USA, 2008.
7. A. Inselberg, The Plane with Parallel Coordinates, Visual Computer, 1, 69–91, 1985.
8. T. K. Maiti and C. K. Maiti, Strained-Engineered MOSFETs: Design and
Optimization Using TCAD, Proceedings of International SiGe Technology and
Device Meeting (ISTDM), Taiwan, Mon-P1-60, 2008.