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Process-Aware Design of Strain-Engineered MOSFETs
This is shown in Figure 10.6(a) and (b) for process-induced strained Si p- and
n-MOSFETs. Input range constraints are as before; V t is minimised. Scenarios
show the optimised device with the variance of the output parameters. It can
be seen that the variance of V t is relatively high compared to the other device
characteristics. It is shown that the final device performance is good and better from a manufacturability perspective.
The above DFM/PCM simulation example demonstrates how to optimise
a process and reduce the process development time by reducing the number
of costly and time-consuming design iterations.
10.6 Summary
With extreme scaling down of MOSFETs in high-volume manufacturing, it
is imperative to develop a systematic TCAD-based methodology to design,
characterise, and optimise manufacturability to increase yield. The process
compact model has been used to find the optimum process conditions to
meet a set of device specifications for strain-engineered MOSFETs. The interactive visual optimisation process using design of experiments in a parallel
coordinate plot allows one to explore device performance criteria. Utilisation
of TCAD tools for process optimisation for an overall design for manufacturing (DFM) solution is discussed.
Review Questions
1. What are the major sources of process variability?
2. What do you mean by intradie and interdie process variability?
Give examples.
3. What are the patterning proximity effects?
4. What are the differences among (a) biaxial strain, (b) high-stress capping layers, and (c) embedded silicon-germanium (e-SiGe)?
5. How do high-k gate dielectric and a metal gate process affect the
process variability?
6. What are design for manufacturability (DFM) and design for
yield (DFY)?
7. Why does industry need yield-centric DFM?
8. Why is process optimisation needed?
9. Describe briefly: (a) sensitivity analysis, (b) uncertainty analysis, and
(c) yield analysis.
10. What is the process window? Describe its importance.
Process-Aware Design of Strain-Engineered MOSFETs
This is shown in Figure 10.6(a) and (b) for process-induced strained Si p- and
n-MOSFETs. Input range constraints are as before; V t is minimised. Scenarios
show the optimised device with the variance of the output parameters. It can
be seen that the variance of V t is relatively high compared to the other device
characteristics. It is shown that the final device performance is good and better from a manufacturability perspective.
The above DFM/PCM simulation example demonstrates how to optimise
a process and reduce the process development time by reducing the number
of costly and time-consuming design iterations.
10.6 Summary
With extreme scaling down of MOSFETs in high-volume manufacturing, it
is imperative to develop a systematic TCAD-based methodology to design,
characterise, and optimise manufacturability to increase yield. The process
compact model has been used to find the optimum process conditions to
meet a set of device specifications for strain-engineered MOSFETs. The interactive visual optimisation process using design of experiments in a parallel
coordinate plot allows one to explore device performance criteria. Utilisation
of TCAD tools for process optimisation for an overall design for manufacturing (DFM) solution is discussed.
Review Questions
1. What are the major sources of process variability?
2. What do you mean by intradie and interdie process variability?
Give examples.
3. What are the patterning proximity effects?
4. What are the differences among (a) biaxial strain, (b) high-stress capping layers, and (c) embedded silicon-germanium (e-SiGe)?
5. How do high-k gate dielectric and a metal gate process affect the
process variability?
6. What are design for manufacturability (DFM) and design for
yield (DFY)?
7. Why does industry need yield-centric DFM?
8. Why is process optimisation needed?
9. Describe briefly: (a) sensitivity analysis, (b) uncertainty analysis, and
(c) yield analysis.
10. What is the process window? Describe its importance.