282
Strain-Engineered MOSFETs
generating a process compact model (PCM), which encapsulates the relationships between input (design) and output parameters. The PCM automatically
correlates design parameters to the tolerances. The ranges are normalised to
1 (see Figure 10.4), with the centre representing the nominal value for each
parameter. The process was optimised with respect to threshold voltage,
channel stress, device current, and transconductance. Parallel coordinate
plots link the simulation results to the design variation. The parameter values and ranges indicate whether the domain has been covered sufficiently.
The yellow region is the constraint of the parameters and the outputs that
satisfy the range of design specifications. Red lines within this region depict
the successful design. For the case study of p-MOSFET threshold voltage
optimisation, we allowed a threshold voltage variation within 0.007–0.243 V.
We put a variation limit on gate length by narrowing the experiment selection, resulting in a 5% lower V t compared to the nominal value. We select
only lower V t , which means reducing on-state voltage.
The optimisation procedure is continued, and finally we perform a
further screening on a germanium mole fraction for process-induced
strain-engineered p-MOSFETs and nitride cap layer for process-induced
strain-engineered n-MOSFET, resulting in a combination that gives a Ge
mole fraction and SiN thickness, generating the optimised V t . By repeating the above optimisation procedure, the device performance may further be improved to obtain V t within 1%. The process conditions satisfying
the specifications for V t indicated by black lines in the parallel coordinate
plot provide information about how well the domain space is covered
with the chosen DoE. Figure 10.5(a) and (b) shows the process compact
model evaluation scenarios for process-induced strain-engineered p- and
n-MOSFETs, respectively.
Figure 10.5(a) is a parallel coordinate plot that links the simulation results
to the design variation of the gate length and germanium mole fraction (Ge)
in the embedded SiGe source/drain region for process-induced strain-engineered p-MOSFETs. Similarly, Figure 10.5(b) is a parallel coordinate plot that
links the simulation results to the design variation of the gate length and
cap layer thickness (SiN) for process-induced strain-engineered n-MOSFETs.
10.5 Manufacturability Optimisation
So far, we only optimised device performance. Let us now add aspects of
manufacturability, that is, the minimisation of the impact of parametric variations. We introduce the resulting variance in device characteristics as an
optimisation constraint.
For each candidate from the performance optimisation, we evaluate the
variance of device characteristics originating from the parametric variance.
Strain-Engineered MOSFETs
generating a process compact model (PCM), which encapsulates the relationships between input (design) and output parameters. The PCM automatically
correlates design parameters to the tolerances. The ranges are normalised to
1 (see Figure 10.4), with the centre representing the nominal value for each
parameter. The process was optimised with respect to threshold voltage,
channel stress, device current, and transconductance. Parallel coordinate
plots link the simulation results to the design variation. The parameter values and ranges indicate whether the domain has been covered sufficiently.
The yellow region is the constraint of the parameters and the outputs that
satisfy the range of design specifications. Red lines within this region depict
the successful design. For the case study of p-MOSFET threshold voltage
optimisation, we allowed a threshold voltage variation within 0.007–0.243 V.
We put a variation limit on gate length by narrowing the experiment selection, resulting in a 5% lower V t compared to the nominal value. We select
only lower V t , which means reducing on-state voltage.
The optimisation procedure is continued, and finally we perform a
further screening on a germanium mole fraction for process-induced
strain-engineered p-MOSFETs and nitride cap layer for process-induced
strain-engineered n-MOSFET, resulting in a combination that gives a Ge
mole fraction and SiN thickness, generating the optimised V t . By repeating the above optimisation procedure, the device performance may further be improved to obtain V t within 1%. The process conditions satisfying
the specifications for V t indicated by black lines in the parallel coordinate
plot provide information about how well the domain space is covered
with the chosen DoE. Figure 10.5(a) and (b) shows the process compact
model evaluation scenarios for process-induced strain-engineered p- and
n-MOSFETs, respectively.
Figure 10.5(a) is a parallel coordinate plot that links the simulation results
to the design variation of the gate length and germanium mole fraction (Ge)
in the embedded SiGe source/drain region for process-induced strain-engineered p-MOSFETs. Similarly, Figure 10.5(b) is a parallel coordinate plot that
links the simulation results to the design variation of the gate length and
cap layer thickness (SiN) for process-induced strain-engineered n-MOSFETs.
10.5 Manufacturability Optimisation
So far, we only optimised device performance. Let us now add aspects of
manufacturability, that is, the minimisation of the impact of parametric variations. We introduce the resulting variance in device characteristics as an
optimisation constraint.
For each candidate from the performance optimisation, we evaluate the
variance of device characteristics originating from the parametric variance.