277
Process-Aware Design of Strain-Engineered MOSFETs
10.3 Designs for Manufacturing and Yield Optimisation
In the following, we discuss a general formulation of the device optimisation
problem that is composed of the selected device design parameters and constraints. Thereafter the idea behind the yield maximisation process is established, and the problem is formalised by the yield maximisation technique.
The approach [4] adapted in subthreshold transistor design consists of
exploiting a 3D parameter design space, constructed by T ox , L g , and N halo .
Hence, the yield optimisation problem is as follows:
Yield P C x
T
L
N
x R
ox
g
h alo
Given:
,
,
,
max
{( ) 1}
3
σ σ σ
=
=
∈
(10.1)
where x = [T ox , L g , N halo ] is the set of design variables, σ i is the standard deviation of the ith design parameter, and C(x) is a Boolean random variable function, defined by the bounds of the critical delay (I onmax ) and the maximum
threshold voltage (V tmax ). C(x) is formulated as
( ) ( ( )
)
( ( )
)
max
m ax
C x
I x I
a nd V x V
on
on
t
t
=
≤
≤
(10.2)
Therefore, P{C(x) = 1} is the probability that a device x = (T ox , L g , N halo ) meets
the performance and power constraints in the presence of variations in the
design parameters.
To solve the optimisation problem, Equation (10.1), the first step is to find
a 3D space, generated by the three device design parameters, bound by the
power and performance constraints. This space is called the feasible region,
F c . In addition, an estimate of the probability of placing a device in F c should
be calculated, that is, the probability that a device x i = (T oxi , L gi ) can satisfy
the desired constraints, on-state drive current (I on ), and threshold voltage
(V t ). To estimate such a probability, P{C(x i ) = 1}, a cube is formed in the 3D
parameter design space, where all points within the cube satisfy the constraints. For clarification, a similar problem with two design variables T ox
and L g is denoted in Figure 10.2. Any point inside this plane represents the
construction strain-engineered MOSFET dimensions, corresponding to the
respective ordered pair (T ox , L g ). A feasible region is defined in terms of the
problem constraints. Any device x i above the V t curve in Figure 10.2 satisfies
the power constraint, and any device below the I onmax curve meets the performance constraint. Therefore, all the devices lying in the intersection of the
defined zones can satisfy both constraints, as depicted by the shaded region
in Figure 10.2.
For the last constraint, the yield maximisation problem is reduced to an
inscribed rectangle that is formed by four corner devices: (T l ox , L l
g ), (T l ox , L u
g ),
(T u ox , L l
g ), and (T u ox , L u
g ) in the 2D feasible region. The centre of the maximum
Process-Aware Design of Strain-Engineered MOSFETs
10.3 Designs for Manufacturing and Yield Optimisation
In the following, we discuss a general formulation of the device optimisation
problem that is composed of the selected device design parameters and constraints. Thereafter the idea behind the yield maximisation process is established, and the problem is formalised by the yield maximisation technique.
The approach [4] adapted in subthreshold transistor design consists of
exploiting a 3D parameter design space, constructed by T ox , L g , and N halo .
Hence, the yield optimisation problem is as follows:
Yield P C x
T
L
N
x R
ox
g
h alo
Given:
,
,
,
max
{( ) 1}
3
σ σ σ
=
=
∈
(10.1)
where x = [T ox , L g , N halo ] is the set of design variables, σ i is the standard deviation of the ith design parameter, and C(x) is a Boolean random variable function, defined by the bounds of the critical delay (I onmax ) and the maximum
threshold voltage (V tmax ). C(x) is formulated as
( ) ( ( )
)
( ( )
)
max
m ax
C x
I x I
a nd V x V
on
on
t
t
=
≤
≤
(10.2)
Therefore, P{C(x) = 1} is the probability that a device x = (T ox , L g , N halo ) meets
the performance and power constraints in the presence of variations in the
design parameters.
To solve the optimisation problem, Equation (10.1), the first step is to find
a 3D space, generated by the three device design parameters, bound by the
power and performance constraints. This space is called the feasible region,
F c . In addition, an estimate of the probability of placing a device in F c should
be calculated, that is, the probability that a device x i = (T oxi , L gi ) can satisfy
the desired constraints, on-state drive current (I on ), and threshold voltage
(V t ). To estimate such a probability, P{C(x i ) = 1}, a cube is formed in the 3D
parameter design space, where all points within the cube satisfy the constraints. For clarification, a similar problem with two design variables T ox
and L g is denoted in Figure 10.2. Any point inside this plane represents the
construction strain-engineered MOSFET dimensions, corresponding to the
respective ordered pair (T ox , L g ). A feasible region is defined in terms of the
problem constraints. Any device x i above the V t curve in Figure 10.2 satisfies
the power constraint, and any device below the I onmax curve meets the performance constraint. Therefore, all the devices lying in the intersection of the
defined zones can satisfy both constraints, as depicted by the shaded region
in Figure 10.2.
For the last constraint, the yield maximisation problem is reduced to an
inscribed rectangle that is formed by four corner devices: (T l ox , L l
g ), (T l ox , L u
g ),
(T u ox , L l
g ), and (T u ox , L u
g ) in the 2D feasible region. The centre of the maximum