275
Process-Aware Design of Strain-Engineered MOSFETs
circuit sensitivity to process variation. Both approaches rely on exploration
through the use of simulation frameworks that capture the detailed interaction between manufacturing variation and the resulting circuit performance
variability. With such a framework, one can determine the most deleterious sources of device parameter variation, and then identify the effects of a
certain flavour of process control, or search for sensitivity-reducing design
techniques.
Yield and performance are the foremost concerns for device design in the
semiconductor industry, and a clear understanding of their sensitivity to
process parameters is the key for better control. In this chapter, we shall
discuss a TCAD methodology that addresses the manufacturing challenges
posed by rising technological complexity, increasing process variability,
and shrinking time-to-market windows. Using TCAD process and device
simulations for typical CMOS technology as input, process compact models
(PCMs) are created to enable efficient analysis of complex and multivariate
process-device relationships. PCMs are then applied to enhance manufacturability and process control. A yield optimisation technique is also proposed to suppress the variability of a device optimised for subthreshold
operation. The goal of this technique is to construct and inscribe a maximum yield region composed of oxide thickness, gate length, cap layer thickness, Ge mole fraction, and channel doping concentration. The centre of this
cube is chosen as the maximum yield design point with the highest immunity against variations. By using the technique, a transistor is optimised to
design an inverter circuit.
10.2 Classifications of Variation
Circuit parametric variations arise either from fluctuations in the wafer
manufacturing process, known as intrinsic variation, or from the dynamic
operation of the circuit, for example, local temperature and supply voltage
variations, known as extrinsic variation. For this discussion, we are concerned with sources of intrinsic variation, although comprehensive models
for intrinsic variation allow circuit simulators to account for extrinsic variation. Figure 10.1 is a chart showing the possible sources of yield loss. Yet,
except for the random defects component and the physics component (such
as stress, electromigration, and reliability), it could have easily been used as
a map of the sources of variability.
Variability occurs as a function of location (spatial) or time (temporal).
Spatial variability can be grouped based on its inherent length scale. Longlength scales, for example, a cross-wafer nonuniformity in etch and deposition processes, lead to interdie variation. On the other hand, short-length
Process-Aware Design of Strain-Engineered MOSFETs
circuit sensitivity to process variation. Both approaches rely on exploration
through the use of simulation frameworks that capture the detailed interaction between manufacturing variation and the resulting circuit performance
variability. With such a framework, one can determine the most deleterious sources of device parameter variation, and then identify the effects of a
certain flavour of process control, or search for sensitivity-reducing design
techniques.
Yield and performance are the foremost concerns for device design in the
semiconductor industry, and a clear understanding of their sensitivity to
process parameters is the key for better control. In this chapter, we shall
discuss a TCAD methodology that addresses the manufacturing challenges
posed by rising technological complexity, increasing process variability,
and shrinking time-to-market windows. Using TCAD process and device
simulations for typical CMOS technology as input, process compact models
(PCMs) are created to enable efficient analysis of complex and multivariate
process-device relationships. PCMs are then applied to enhance manufacturability and process control. A yield optimisation technique is also proposed to suppress the variability of a device optimised for subthreshold
operation. The goal of this technique is to construct and inscribe a maximum yield region composed of oxide thickness, gate length, cap layer thickness, Ge mole fraction, and channel doping concentration. The centre of this
cube is chosen as the maximum yield design point with the highest immunity against variations. By using the technique, a transistor is optimised to
design an inverter circuit.
10.2 Classifications of Variation
Circuit parametric variations arise either from fluctuations in the wafer
manufacturing process, known as intrinsic variation, or from the dynamic
operation of the circuit, for example, local temperature and supply voltage
variations, known as extrinsic variation. For this discussion, we are concerned with sources of intrinsic variation, although comprehensive models
for intrinsic variation allow circuit simulators to account for extrinsic variation. Figure 10.1 is a chart showing the possible sources of yield loss. Yet,
except for the random defects component and the physics component (such
as stress, electromigration, and reliability), it could have easily been used as
a map of the sources of variability.
Variability occurs as a function of location (spatial) or time (temporal).
Spatial variability can be grouped based on its inherent length scale. Longlength scales, for example, a cross-wafer nonuniformity in etch and deposition processes, lead to interdie variation. On the other hand, short-length