274
Strain-Engineered MOSFETs
with lower scaling factors, including non-CMOS devices, are expected. This
results in a greater variability. For example, the gate dielectric of a typical
65 nm node is on the order of four atomic layers thick. It would be impossible for any process to place four atomic layers precisely on the gate oxide of
every transistor on an entire wafer. Also, with gate length CDs in the sub-40
nm range, 4 nm of variability would represent a 10% change in the CDs [3].
As variability in manufacturing processes has grown more severe, variations in device parameter values have grown in proportion to nominal values. In turn, wider distributions for device parameters have led to increased
variability in circuit performance, causing worsened yield degradation in
successive technology generations.
Technology computer-aided design (TCAD) tools can simulate IC fabrication process technology and device characteristics and are indispensable for
advanced technology development and manufacturing. TCAD is now an
integral part of integrated circuit manufacturing due to its predictive capability for the process, device, and circuit simulations. TCAD also has the
power to analyse accurately the impact of process parameter variations on
device characteristics and may be used to address and control process variability as needed for modelling the semiconductor manufacturing process.
In this chapter, a systematic study based on technology CAD is taken up
for the optimisation of strain-engineered metal-oxide-semiconductor fieldeffect transistors (MOSFETs) in Si CMOS technology via virtual wafer fabrication (VWF). A simple and manufacturable process recipe is developed to
induce uniaxial stress in the channel region to obtain enhanced performance
in the CMOS.
10.1 Process Design Co-Optimisation
The general flow for fabrication of integrated circuits is comprised of several steps. In the front-end processes, dopants are implanted and diffused
into the silicon substrate and various materials are repeatedly deposited
and patterned to build active devices such as MOS transistors. In back-end
processes, layers of interconnects used as wires between active devices are
created using successive repetitions of deposition, patterning, and polishing. Variability in circuit performance is a rapidly growing concern in the
semiconductor industry, and a potential roadblock in circuit design. To avoid
the negative impact of manufacturing variations on circuit performance, two
approaches are being taken. The first approach is to apply a renewed focus
on process control from a manufacturing perspective, in an effort to directly
reduce the variations in device parameters. The second approach comes
from the design perspective, where practises can be developed to decrease
Strain-Engineered MOSFETs
with lower scaling factors, including non-CMOS devices, are expected. This
results in a greater variability. For example, the gate dielectric of a typical
65 nm node is on the order of four atomic layers thick. It would be impossible for any process to place four atomic layers precisely on the gate oxide of
every transistor on an entire wafer. Also, with gate length CDs in the sub-40
nm range, 4 nm of variability would represent a 10% change in the CDs [3].
As variability in manufacturing processes has grown more severe, variations in device parameter values have grown in proportion to nominal values. In turn, wider distributions for device parameters have led to increased
variability in circuit performance, causing worsened yield degradation in
successive technology generations.
Technology computer-aided design (TCAD) tools can simulate IC fabrication process technology and device characteristics and are indispensable for
advanced technology development and manufacturing. TCAD is now an
integral part of integrated circuit manufacturing due to its predictive capability for the process, device, and circuit simulations. TCAD also has the
power to analyse accurately the impact of process parameter variations on
device characteristics and may be used to address and control process variability as needed for modelling the semiconductor manufacturing process.
In this chapter, a systematic study based on technology CAD is taken up
for the optimisation of strain-engineered metal-oxide-semiconductor fieldeffect transistors (MOSFETs) in Si CMOS technology via virtual wafer fabrication (VWF). A simple and manufacturable process recipe is developed to
induce uniaxial stress in the channel region to obtain enhanced performance
in the CMOS.
10.1 Process Design Co-Optimisation
The general flow for fabrication of integrated circuits is comprised of several steps. In the front-end processes, dopants are implanted and diffused
into the silicon substrate and various materials are repeatedly deposited
and patterned to build active devices such as MOS transistors. In back-end
processes, layers of interconnects used as wires between active devices are
created using successive repetitions of deposition, patterning, and polishing. Variability in circuit performance is a rapidly growing concern in the
semiconductor industry, and a potential roadblock in circuit design. To avoid
the negative impact of manufacturing variations on circuit performance, two
approaches are being taken. The first approach is to apply a renewed focus
on process control from a manufacturing perspective, in an effort to directly
reduce the variations in device parameters. The second approach comes
from the design perspective, where practises can be developed to decrease