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Strain-Engineered MOSFETs
design and virtual wafer fabrication (VWF) of strain-engineered MOSFETs
in Si CMOS technology. A manufacturable process has been considered to
induce uniaxial stress in the channel region to obtain enhanced CMOS performance. A methodology for capturing process variability in SPICE models
has been presented. Process parameters considered are gate length (L g ), gate
oxidation temperature, halo dose, cap layer thickness, Ge mole fraction, and
V th implant dose. The methodology involves global extraction of processdependent SPICE model parameters from strained Si calibrated TCAD
simulations. The model is validated by comparing device characteristics
from the extracted SPICE parameters with those from TCAD simulations.
The SPICE parameters are used to identify the impact of process variability
on critical circuit performance. The extracted models are employed in an
inverter circuit with strain-engineered MOSFETs. The process-dependent
SPICE models extracted from Paramos provide a key bidirectional link
between the variability of the manufacturing process and circuit simulations of chip performance.
Review Questions
1. Compare physically based, semiempirical, empirical, and compact models.
2. Describe briefly the applications of the SPICE simulation tool.
3. What is the predictive technology model?
4. Describe briefly the applications of PTM.
5. What is meant by process compact SPICE model?
6. Compare the process compact model with the standard SPICE model.
7. What are the latest versions of the process compact SPICE model and
standard SPICE model?
8. Describe the PCM methodology.
9. Write the steps to be followed to determine the process-dependent
SPICE parameters for the process parameter variations, such as gate
critical dimension, annealing, and implantation.
10. Describe briefly: (a) worst-case corner models, (b) statistical corner
models, and (c) TCAD-based corner models.
11. Describe the predictability of the BSIM model for the process and
layout variation.
12. What are the impacts of PCM for circuit-level analysis?
Strain-Engineered MOSFETs
design and virtual wafer fabrication (VWF) of strain-engineered MOSFETs
in Si CMOS technology. A manufacturable process has been considered to
induce uniaxial stress in the channel region to obtain enhanced CMOS performance. A methodology for capturing process variability in SPICE models
has been presented. Process parameters considered are gate length (L g ), gate
oxidation temperature, halo dose, cap layer thickness, Ge mole fraction, and
V th implant dose. The methodology involves global extraction of processdependent SPICE model parameters from strained Si calibrated TCAD
simulations. The model is validated by comparing device characteristics
from the extracted SPICE parameters with those from TCAD simulations.
The SPICE parameters are used to identify the impact of process variability
on critical circuit performance. The extracted models are employed in an
inverter circuit with strain-engineered MOSFETs. The process-dependent
SPICE models extracted from Paramos provide a key bidirectional link
between the variability of the manufacturing process and circuit simulations of chip performance.
Review Questions
1. Compare physically based, semiempirical, empirical, and compact models.
2. Describe briefly the applications of the SPICE simulation tool.
3. What is the predictive technology model?
4. Describe briefly the applications of PTM.
5. What is meant by process compact SPICE model?
6. Compare the process compact model with the standard SPICE model.
7. What are the latest versions of the process compact SPICE model and
standard SPICE model?
8. Describe the PCM methodology.
9. Write the steps to be followed to determine the process-dependent
SPICE parameters for the process parameter variations, such as gate
critical dimension, annealing, and implantation.
10. Describe briefly: (a) worst-case corner models, (b) statistical corner
models, and (c) TCAD-based corner models.
11. Describe the predictability of the BSIM model for the process and
layout variation.
12. What are the impacts of PCM for circuit-level analysis?