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Process Compact Modelling of Strain-Engineered MOSFETs
References
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Science + Business Media, LLC, New York, USA, 2011.
2. W. Zhao, Predictive Technology Modelling for Scaled CMOS, PhD thesis,
Arizona State University, 2009.
3. W. Zhao and Y. Cao, New Generation of Predictive Technology Model for Sub45 nm Early Design Exploration, IEEE Trans. Electron Dev., 53, 2816–2823, 2006.
4. BSIM4 User Guide, University of California, Berkeley, 2008.
5. X. Li, W. Zhao, Y. Cao, Z. Zhu, J. Song, D. Bang, C.-C. Wang, S. H. Kang, J. Wang,
M. Nowak, and N. Yu, Pathfinding for 22nm CMOS Designs Using Predictive
Technology Models, Proc. Custom Integrated Circuits Conference (CICC’09), 227–
230, 2009.
6. S. Krishnamurthy, V. K. Dasarapu, Y. Mahotin, R. Ryles, F. Roger, S. Uppal,
P. Mukherjee, A. Cuthbertson, and X.-W. Lin, Si-Based Process Aware SPICE
Models for Statistical Circuit Analysis, Proc. Nanotechnol., 3, 897–900, 2008.
7. T. K. Maiti, S. S. Mahato, P. Chakraborty, S. K. Sarkar, and C. K. Maiti, Scaling of
Strain-Engineered MOSFETs, IETE J. Res., 53, 263–236, 2007.
8. C. K. Maiti, T. K. Maiti, and S. S. Mahato, Strain-Engineered MOSFETs,
Semiconductor India Mag., June 2008.
9. R. Borges, T. Ma, W.-C. Ng, S. Krishnamurthy, and L. Bomholt, Implementation
of TCAD-for-Manufacturing Methodology Using Process Compact Models,
Proceedings of International Conference on Solid-State and Integrated Circuit
Technology (ICSI’06), 2006.
10. Synopsys, Inc., Paramos User Guide, version B-2008.06, Mountain View, CA,
June 2008.
11. S. Tirumala, Y. Mahotin, X. Lin, V. Moroz, L. Smith, S. Krishnamurthy, L.
Bomholt, and D. Pramanik, Bringing Manufacturing into Design via ProcessDependent SPICE Models, Proc. Int. Symp. Qual. Electronic Design (ISQED’06),
806–810, 2006.
12. Synopsys, Inc., HSPICE User Guide: Simulation and Analysis, version C-2009.03,
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Process Compact Modelling of Strain-Engineered MOSFETs
References
1. Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer
Science + Business Media, LLC, New York, USA, 2011.
2. W. Zhao, Predictive Technology Modelling for Scaled CMOS, PhD thesis,
Arizona State University, 2009.
3. W. Zhao and Y. Cao, New Generation of Predictive Technology Model for Sub45 nm Early Design Exploration, IEEE Trans. Electron Dev., 53, 2816–2823, 2006.
4. BSIM4 User Guide, University of California, Berkeley, 2008.
5. X. Li, W. Zhao, Y. Cao, Z. Zhu, J. Song, D. Bang, C.-C. Wang, S. H. Kang, J. Wang,
M. Nowak, and N. Yu, Pathfinding for 22nm CMOS Designs Using Predictive
Technology Models, Proc. Custom Integrated Circuits Conference (CICC’09), 227–
230, 2009.
6. S. Krishnamurthy, V. K. Dasarapu, Y. Mahotin, R. Ryles, F. Roger, S. Uppal,
P. Mukherjee, A. Cuthbertson, and X.-W. Lin, Si-Based Process Aware SPICE
Models for Statistical Circuit Analysis, Proc. Nanotechnol., 3, 897–900, 2008.
7. T. K. Maiti, S. S. Mahato, P. Chakraborty, S. K. Sarkar, and C. K. Maiti, Scaling of
Strain-Engineered MOSFETs, IETE J. Res., 53, 263–236, 2007.
8. C. K. Maiti, T. K. Maiti, and S. S. Mahato, Strain-Engineered MOSFETs,
Semiconductor India Mag., June 2008.
9. R. Borges, T. Ma, W.-C. Ng, S. Krishnamurthy, and L. Bomholt, Implementation
of TCAD-for-Manufacturing Methodology Using Process Compact Models,
Proceedings of International Conference on Solid-State and Integrated Circuit
Technology (ICSI’06), 2006.
10. Synopsys, Inc., Paramos User Guide, version B-2008.06, Mountain View, CA,
June 2008.
11. S. Tirumala, Y. Mahotin, X. Lin, V. Moroz, L. Smith, S. Krishnamurthy, L.
Bomholt, and D. Pramanik, Bringing Manufacturing into Design via ProcessDependent SPICE Models, Proc. Int. Symp. Qual. Electronic Design (ISQED’06),
806–810, 2006.
12. Synopsys, Inc., HSPICE User Guide: Simulation and Analysis, version C-2009.03,
Mountain View, CA, 2009.