259
Process Compact Modelling of Strain-Engineered MOSFETs
effects. The customised PTM models have been calibrated to 90 to 45 nm
Poly/SiON silicon and high-k/metal gate (HK-MG) data.
9.2.1 PTM for FinFET
Beyond the 22 nm technology node, more radical solutions will be necessary
to meet the scaling criteria for off-state leakage. The double-gate MOSFET
(DG) or FinFET is regarded as a promising alternative device for the nanoscale
design because of its improved scalability and the effective suppression of
short-channel effects. When the body silicon thickness (T Si ) is sufficiently
thinner than the channel length, short-channel effects, such as V th lowering, DIBL, and increased subthreshold swing, can be effectively suppressed.
With a lightly doped channel, the threshold voltage of a FinFET transistor is
weakly affected by random dopant fluctuations. The FinFET device is electrostatically more robust than bulk CMOS since two gates are used to control
the channel. The front and back gates can be connected together or biased
independently, using the front gate to switch the transistor on/off and the
back gate as a control signal. At the 32 nm node, it may improve the I on /I off
ratio by more than 100%. About 20 sets of published I-V data from the 250 nm
node to the 45 nm node at room temperature were used to verify the PTM for
FinFETs. By tuning 10 primary parameters, the predicted I-V characteristics
are compared for verification. Figure 9.11 demonstrates the matching of a
FinFET transistor with L eff = 30 nm.
9.3 Process-Aware Design for Manufacturing
As the CMOS technology continues to scale down in the sub-100 nm regime,
power dissipation and robustness of a circuit with respect to process variations pose major design challenges. Variability arising from advanced silicon technologies, such as strain engineering, is increasingly affecting the
circuit performance. The control of process fluctuations has not kept pace
with rapidly shrinking device dimensions. It is important to characterise
and quantify systematic, random, die-to-die, and within-die transistor variability in order to control variability from both the manufacturing and the
design angle. Variation-aware statistical analysis technologies are needed to
explore and optimise the process and design methodologies. The Paramos
tool from Synopsys links SPICE models directly to manufacturing conditions by extracting process-aware SPICE compact models that combine calibrated TCAD simulations with global SPICE extraction. It allows users to
simulate the impact of process variability (statistical or systematic) on circuit
performance. This methodology also provides a physically based variation
model for statistical timing simulations of circuit performance, allowing
Process Compact Modelling of Strain-Engineered MOSFETs
effects. The customised PTM models have been calibrated to 90 to 45 nm
Poly/SiON silicon and high-k/metal gate (HK-MG) data.
9.2.1 PTM for FinFET
Beyond the 22 nm technology node, more radical solutions will be necessary
to meet the scaling criteria for off-state leakage. The double-gate MOSFET
(DG) or FinFET is regarded as a promising alternative device for the nanoscale
design because of its improved scalability and the effective suppression of
short-channel effects. When the body silicon thickness (T Si ) is sufficiently
thinner than the channel length, short-channel effects, such as V th lowering, DIBL, and increased subthreshold swing, can be effectively suppressed.
With a lightly doped channel, the threshold voltage of a FinFET transistor is
weakly affected by random dopant fluctuations. The FinFET device is electrostatically more robust than bulk CMOS since two gates are used to control
the channel. The front and back gates can be connected together or biased
independently, using the front gate to switch the transistor on/off and the
back gate as a control signal. At the 32 nm node, it may improve the I on /I off
ratio by more than 100%. About 20 sets of published I-V data from the 250 nm
node to the 45 nm node at room temperature were used to verify the PTM for
FinFETs. By tuning 10 primary parameters, the predicted I-V characteristics
are compared for verification. Figure 9.11 demonstrates the matching of a
FinFET transistor with L eff = 30 nm.
9.3 Process-Aware Design for Manufacturing
As the CMOS technology continues to scale down in the sub-100 nm regime,
power dissipation and robustness of a circuit with respect to process variations pose major design challenges. Variability arising from advanced silicon technologies, such as strain engineering, is increasingly affecting the
circuit performance. The control of process fluctuations has not kept pace
with rapidly shrinking device dimensions. It is important to characterise
and quantify systematic, random, die-to-die, and within-die transistor variability in order to control variability from both the manufacturing and the
design angle. Variation-aware statistical analysis technologies are needed to
explore and optimise the process and design methodologies. The Paramos
tool from Synopsys links SPICE models directly to manufacturing conditions by extracting process-aware SPICE compact models that combine calibrated TCAD simulations with global SPICE extraction. It allows users to
simulate the impact of process variability (statistical or systematic) on circuit
performance. This methodology also provides a physically based variation
model for statistical timing simulations of circuit performance, allowing