258
Strain-Engineered MOSFETs
Second to L eff variation, the impact of N ch variation also keeps increasing as
technology scales. Figure 9.9 shows the decomposition of the impact of L eff
variations during technology scaling. It reveals that velocity overshoot plays
a more important role than DIBL for nanoscale MOSFET. Therefore, physical
modelling of velocity overshoot is necessary in variation-aware design. Since
PTM can be easily customised by tuning L eff , T 0xe , R dsw , V th0 , E ta0 , V dd , and other
primary parameters, robust circuit design research under different conditions is fully supported.
PTM models gate tunneling leakage relying on scalable models of leakage
current. Calibration with published 65 and 45 nm data has shown a reduction
by about 25–1,000 times in gate tunneling leakage for the same EOT. It has been
shown that HK-MG technology will not only suppress gate leakage, but also
boost driving current significantly. Figure 9.10 shows the smooth predictions of
I on and I off at the 32 nm node with and without HK-MG for all three V th processes.
I off of high V th deviates from the nominal trend due to the GIDL and tunneling
current. Besides the prediction of I-V, the scaling trends of gate and parasitic
capacitances are covered in PTM, since they are important for dynamic circuit
performance. PTM validation shows a smooth prediction of both speed and
power consumption from the 65 nm node down to the 32 nm node.
Li et al. [5] have proposed a predictive strategy for simultaneous exploration of low-power CMOS process and design concepts for 22 nm low-power
designs. Authors have evaluated critical performance metrics, e.g., speed
and power, with various technological components and design choices with
scaled CMOS and have incorporated the general PTM methodology, with
customised enhancements of transistor-level and interconnect-level physical
FIGURE 9.10
I on and I off predictions at the 32 nm node for various process choices. (After Zhao, W., Predictive
Technology Modelling for Scaled CMOS, PhD thesis, Arizona State University, 2009.)
Strain-Engineered MOSFETs
Second to L eff variation, the impact of N ch variation also keeps increasing as
technology scales. Figure 9.9 shows the decomposition of the impact of L eff
variations during technology scaling. It reveals that velocity overshoot plays
a more important role than DIBL for nanoscale MOSFET. Therefore, physical
modelling of velocity overshoot is necessary in variation-aware design. Since
PTM can be easily customised by tuning L eff , T 0xe , R dsw , V th0 , E ta0 , V dd , and other
primary parameters, robust circuit design research under different conditions is fully supported.
PTM models gate tunneling leakage relying on scalable models of leakage
current. Calibration with published 65 and 45 nm data has shown a reduction
by about 25–1,000 times in gate tunneling leakage for the same EOT. It has been
shown that HK-MG technology will not only suppress gate leakage, but also
boost driving current significantly. Figure 9.10 shows the smooth predictions of
I on and I off at the 32 nm node with and without HK-MG for all three V th processes.
I off of high V th deviates from the nominal trend due to the GIDL and tunneling
current. Besides the prediction of I-V, the scaling trends of gate and parasitic
capacitances are covered in PTM, since they are important for dynamic circuit
performance. PTM validation shows a smooth prediction of both speed and
power consumption from the 65 nm node down to the 32 nm node.
Li et al. [5] have proposed a predictive strategy for simultaneous exploration of low-power CMOS process and design concepts for 22 nm low-power
designs. Authors have evaluated critical performance metrics, e.g., speed
and power, with various technological components and design choices with
scaled CMOS and have incorporated the general PTM methodology, with
customised enhancements of transistor-level and interconnect-level physical
FIGURE 9.10
I on and I off predictions at the 32 nm node for various process choices. (After Zhao, W., Predictive
Technology Modelling for Scaled CMOS, PhD thesis, Arizona State University, 2009.)