252
Strain-Engineered MOSFETs
technology scales. Accurate and efficient modelling of back-end-of-line
interconnect paratactic capacitance is essential in determining various onchip interconnect-related issues such as delay, cross talk, resistive drop, and
power dissipation. As CMOS technology continues scaling, metal wiring
pitch concurs to shrink with transistor feature size to increase chip density.
This makes BEOL metal wiring line capacitance (c) and resistance (R), i.e., the
RC delay, difficult to be reduced fast enough, compared to the ever-increasing FEOL transistor speed. As a result, the interconnect parasitic becomes a
limiting factor in circuit performance. Meanwhile, the interconnect structure becomes increasingly complex, and nonuniform dielectrics, such as stop
layer and air gap, are being used. To efficiently extract the paratactic of interconnects, a compact capacitance model is developed.
The predictive technology model, which was initiated at the University of
California, Berkeley, in 1999, bridges process development and circuit design
through device modelling, and is essential for supporting early design prototyping. PTM is a critical interface between technology innovation and IC
design exploration [2]. PTM introduces scalable models for strained Si, multiple V th , and HK-MG processes, and even the FinFET structures. Primary
parameters under the influence of these technology enhancements include
the increase of mobility, the control of SCE, and the coupling between front
and back gates in a FinFET device. PTM quantitatively evaluates various
technology factors in scaled CMOS design, helping prediction on the performance trend along the road map. PTM has been used for a 45 nm predictive process design kit (PDK), which is the critical interface between circuit
design and silicon fabrication.
Initially, PTM was proposed to help bridge the technology and design
groups, such that these issues could be brought to attention as early as possible in the design process. The current Berkeley Predictive Technology
Model (BPTM), based on the BSIM4 model, includes more physical parameters and provides a standard compact model down to the 12 nm technology
node [1]. Recently PTM has been extended from conventional CMOS devices
to advanced devices, including strained Si, HK-MG, and the double-gate
structures. To predict future technology characteristics, however, a simple
approach to scale down the geometry and voltages from an existing technology does not work. For example, a comparison of predicted device data based
on a well-characterised 130 nm technology, when scaled down in terms of
L eff , T ox , V th0 , R dsw , and V dd for an early 65 nm technology device, shows an
overall performance underestimation (Figure 9.1).
Although there are typically more than 100 parameters in a compact transistor model to calculate the current-voltage (I-V) and capacitance-voltage
(C-V) characteristics, only about 10 of them are critical to determine the essential behaviour of nanoscale transistors. The accuracy of PTM predictions has
been verified with published silicon data; an error in I on is below 10% for both
n- and p-MOSFET devices. By tuning only 10 primary model parameters,
Strain-Engineered MOSFETs
technology scales. Accurate and efficient modelling of back-end-of-line
interconnect paratactic capacitance is essential in determining various onchip interconnect-related issues such as delay, cross talk, resistive drop, and
power dissipation. As CMOS technology continues scaling, metal wiring
pitch concurs to shrink with transistor feature size to increase chip density.
This makes BEOL metal wiring line capacitance (c) and resistance (R), i.e., the
RC delay, difficult to be reduced fast enough, compared to the ever-increasing FEOL transistor speed. As a result, the interconnect parasitic becomes a
limiting factor in circuit performance. Meanwhile, the interconnect structure becomes increasingly complex, and nonuniform dielectrics, such as stop
layer and air gap, are being used. To efficiently extract the paratactic of interconnects, a compact capacitance model is developed.
The predictive technology model, which was initiated at the University of
California, Berkeley, in 1999, bridges process development and circuit design
through device modelling, and is essential for supporting early design prototyping. PTM is a critical interface between technology innovation and IC
design exploration [2]. PTM introduces scalable models for strained Si, multiple V th , and HK-MG processes, and even the FinFET structures. Primary
parameters under the influence of these technology enhancements include
the increase of mobility, the control of SCE, and the coupling between front
and back gates in a FinFET device. PTM quantitatively evaluates various
technology factors in scaled CMOS design, helping prediction on the performance trend along the road map. PTM has been used for a 45 nm predictive process design kit (PDK), which is the critical interface between circuit
design and silicon fabrication.
Initially, PTM was proposed to help bridge the technology and design
groups, such that these issues could be brought to attention as early as possible in the design process. The current Berkeley Predictive Technology
Model (BPTM), based on the BSIM4 model, includes more physical parameters and provides a standard compact model down to the 12 nm technology
node [1]. Recently PTM has been extended from conventional CMOS devices
to advanced devices, including strained Si, HK-MG, and the double-gate
structures. To predict future technology characteristics, however, a simple
approach to scale down the geometry and voltages from an existing technology does not work. For example, a comparison of predicted device data based
on a well-characterised 130 nm technology, when scaled down in terms of
L eff , T ox , V th0 , R dsw , and V dd for an early 65 nm technology device, shows an
overall performance underestimation (Figure 9.1).
Although there are typically more than 100 parameters in a compact transistor model to calculate the current-voltage (I-V) and capacitance-voltage
(C-V) characteristics, only about 10 of them are critical to determine the essential behaviour of nanoscale transistors. The accuracy of PTM predictions has
been verified with published silicon data; an error in I on is below 10% for both
n- and p-MOSFET devices. By tuning only 10 primary model parameters,