251
Process Compact Modelling of Strain-Engineered MOSFETs
not systematic. Interdie variations are systematic and affect adjacent transistors on a chip with equal shift from nominal value. Intradie variations are
random variations and affect adjacent transistors on the same chip with different shifts.
9.2 Predictive Technology Modelling
To continue the design success with nanoscale CMOS, one requires an
early comprehension of the technology impacts on circuit design. Although
high-k/metal gate and strained silicon techniques have helped extend the
CMOS technology, they have also complicated the fabrication process and
increased the amount of process variations. Aggressive technology scaling has led to large uncertainties in device and interconnect characteristics for deep-submicron circuits. Many physical phenomena, unforeseen in
the larger dimensions, such as short-channel effect (SCE) and exponential
increase in leakage, are becoming the major bottlenecks for continuous technology scaling. Increasing variations (both interdie and intradie) in device
parameters (channel length, gate width, oxide thickness, device threshold
voltage, etc.) produce a large spread in the delay and power consumption in
advanced integrated circuits. The presence of large process variations and
deep-submicron effects requires a paradigm change in the design and optimisation of large-scale circuits and systems. It is important to link the process parameters, including the distribution to SPICE parameters, to study
the global variations at the circuit level. By using accurate physical models of
the manufacturing process, custom designers can account for manufacturing variability.
For circuit design, it is critical to have predictive MOSFET models that are
reasonably accurate, scalable, and correctly capture the new physical effects
arising out of the nanoscale CMOS technology. Examples of the emerging
challenges include leakage current, process variations, and transistor reliability. The predictive technology model (PTM) is critical for early circuit
design research to assess performance trends and evaluate key modules to
facilitate the development of future CMOS technology. It is currently being
used to predict the characteristics of nanoscale CMOS, including physical
effects, process variations, and physical correlations among model parameters. A new generation of predictive technology models for front-end-ofthe-line (FEOL) CMOS technology has been developed from the 250 nm to
32 nm nodes, including both high-performance and low-power processes
and alternative structures such as FinFET and high-k/metal gate (HK-MG)
based on the Berkeley Predictive Technology Model (BPTM) [1].
Back-end-of-line (BEOL) interconnects become a limiting factor in circuit performance as complementary metal-oxide-semiconductor (CMOS)
Process Compact Modelling of Strain-Engineered MOSFETs
not systematic. Interdie variations are systematic and affect adjacent transistors on a chip with equal shift from nominal value. Intradie variations are
random variations and affect adjacent transistors on the same chip with different shifts.
9.2 Predictive Technology Modelling
To continue the design success with nanoscale CMOS, one requires an
early comprehension of the technology impacts on circuit design. Although
high-k/metal gate and strained silicon techniques have helped extend the
CMOS technology, they have also complicated the fabrication process and
increased the amount of process variations. Aggressive technology scaling has led to large uncertainties in device and interconnect characteristics for deep-submicron circuits. Many physical phenomena, unforeseen in
the larger dimensions, such as short-channel effect (SCE) and exponential
increase in leakage, are becoming the major bottlenecks for continuous technology scaling. Increasing variations (both interdie and intradie) in device
parameters (channel length, gate width, oxide thickness, device threshold
voltage, etc.) produce a large spread in the delay and power consumption in
advanced integrated circuits. The presence of large process variations and
deep-submicron effects requires a paradigm change in the design and optimisation of large-scale circuits and systems. It is important to link the process parameters, including the distribution to SPICE parameters, to study
the global variations at the circuit level. By using accurate physical models of
the manufacturing process, custom designers can account for manufacturing variability.
For circuit design, it is critical to have predictive MOSFET models that are
reasonably accurate, scalable, and correctly capture the new physical effects
arising out of the nanoscale CMOS technology. Examples of the emerging
challenges include leakage current, process variations, and transistor reliability. The predictive technology model (PTM) is critical for early circuit
design research to assess performance trends and evaluate key modules to
facilitate the development of future CMOS technology. It is currently being
used to predict the characteristics of nanoscale CMOS, including physical
effects, process variations, and physical correlations among model parameters. A new generation of predictive technology models for front-end-ofthe-line (FEOL) CMOS technology has been developed from the 250 nm to
32 nm nodes, including both high-performance and low-power processes
and alternative structures such as FinFET and high-k/metal gate (HK-MG)
based on the Berkeley Predictive Technology Model (BPTM) [1].
Back-end-of-line (BEOL) interconnects become a limiting factor in circuit performance as complementary metal-oxide-semiconductor (CMOS)