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Strain-Engineered MOSFETs
constructing compact SPICE models as a function of process parameter
variations. We present a simulation methodology for strain-engineered
metal-oxide-semiconductor field-effect transistors (MOSFETs), which allow
the flow of pertinent information between process and design engineers
without the need for disclosing the details of process technology. The methodology involves global extraction of process-dependent SPICE model
parameters. Linking design and process, statistical compact models provide
the essential correlation between performance statistics and process parameter statistics.
9.1 Process Variation
Process variations refer to those variations caused due to the imperfections
in different steps of the manufacturing process; these could be due to the
limited resolution of the photolithographic stage within the fabrication
process, which results in variations in the width and length of transistors
on the chip. It could also be from nonuniform conditions during the diffusion stage, in which impurities are introduced. These imperfections cause
variations in the electrical properties of the transistors and interconnect on
the chip from their designed values. Examples are variations in the geometries of the transistors (e.g., effective channel length, oxide thickness), or
due to random dopant fluctuations (affecting the threshold voltage of the
transistors).
In general, the process variations can be distinguished into the following components:
1. Die-to-die (interdie) variation: These are largely independent of
design implementation and cause systematic variations in electrical
characteristics within the chip.
2. Within-die (intradie) variations. These can be distinguished into
four subcategories:
a. Wafer-level variations due to nonuniformities (e.g., thermal gradient)
b. Die-level variations caused by imperfections in mask making/
lithography
c. Wafer-die interaction on account of dependence due to chip location within the wafer
d. Random residuals due to random dopant fluctuation, etc.
The first three are correlated systematic components, whereas the last one
forms the uncorrelated random component in intradie process variation.
Intradie variations are more difficult to solve because these variations are
Strain-Engineered MOSFETs
constructing compact SPICE models as a function of process parameter
variations. We present a simulation methodology for strain-engineered
metal-oxide-semiconductor field-effect transistors (MOSFETs), which allow
the flow of pertinent information between process and design engineers
without the need for disclosing the details of process technology. The methodology involves global extraction of process-dependent SPICE model
parameters. Linking design and process, statistical compact models provide
the essential correlation between performance statistics and process parameter statistics.
9.1 Process Variation
Process variations refer to those variations caused due to the imperfections
in different steps of the manufacturing process; these could be due to the
limited resolution of the photolithographic stage within the fabrication
process, which results in variations in the width and length of transistors
on the chip. It could also be from nonuniform conditions during the diffusion stage, in which impurities are introduced. These imperfections cause
variations in the electrical properties of the transistors and interconnect on
the chip from their designed values. Examples are variations in the geometries of the transistors (e.g., effective channel length, oxide thickness), or
due to random dopant fluctuations (affecting the threshold voltage of the
transistors).
In general, the process variations can be distinguished into the following components:
1. Die-to-die (interdie) variation: These are largely independent of
design implementation and cause systematic variations in electrical
characteristics within the chip.
2. Within-die (intradie) variations. These can be distinguished into
four subcategories:
a. Wafer-level variations due to nonuniformities (e.g., thermal gradient)
b. Die-level variations caused by imperfections in mask making/
lithography
c. Wafer-die interaction on account of dependence due to chip location within the wafer
d. Random residuals due to random dopant fluctuation, etc.
The first three are correlated systematic components, whereas the last one
forms the uncorrelated random component in intradie process variation.
Intradie variations are more difficult to solve because these variations are