249
9
Process Compact Modelling of
Strain-Engineered MOSFETs
As complementary metal-oxide-semiconductor (CMOS) downscaling approaches the manufacturing limits, process variability and reliability degradation become the key limiting factors for future integrated circuits and
systems design. At nanoscale, physical factors that previously had little or no
impact on circuit performance are now becoming increasingly significant.
Examples include process variations, transistor mobility degradation, and
power consumption. These new effects pose dramatic challenges to robust circuit design and system integration. Process variations have become increasingly important for scaled technologies starting at 45 nm, as nontraditional
materials and structures and even strain technology are being introduced to
enhance the device performance. Use of strain technology in manufacturing has urged that the designers assess layout-dependent effects and manage their impact. Thus, the demand of predictive modelling becomes even
stronger as we face more complicated and diverse technological choices for
larger-scale integration. High process variability not only affects the circuit
performance but also reduces manufacturing yield. To improve manufacturing yield of technologies 45 nm and below, performance variability should
be considered during the design phase. In the conventional design approach,
high variability leads to overdesigning, thereby increasing area and power
consumption. To avoid overdesigning, accurate estimation of variability is
required.
According to the International Technology Roadmap for Semiconductors
(ITRS), for technology nodes beyond 45 nm, larger amounts of process variations are expected. The increased variations are primarily due to random
dopant fluctuations, line-edge roughness, and oxide thickness fluctuation.
These variations greatly impact all aspects of circuit performance and pose
a great challenge to future integrated circuit (IC) design. To improve robustness, efficient methodology is required that considers the effect of variations
in the design flow. What matters is not only the amount of variations, but
also the sensitivity to variations. At the nanoscale, the sensitivity of transistor performance on process variations becomes more significant and is critical for robust CMOS design.
This chapter covers both the modelling principles and the applications
of predictive technology modelling (PTM) and process compact modelling (PCM) in microelectronics design. We discuss the methodology for
9
Process Compact Modelling of
Strain-Engineered MOSFETs
As complementary metal-oxide-semiconductor (CMOS) downscaling approaches the manufacturing limits, process variability and reliability degradation become the key limiting factors for future integrated circuits and
systems design. At nanoscale, physical factors that previously had little or no
impact on circuit performance are now becoming increasingly significant.
Examples include process variations, transistor mobility degradation, and
power consumption. These new effects pose dramatic challenges to robust circuit design and system integration. Process variations have become increasingly important for scaled technologies starting at 45 nm, as nontraditional
materials and structures and even strain technology are being introduced to
enhance the device performance. Use of strain technology in manufacturing has urged that the designers assess layout-dependent effects and manage their impact. Thus, the demand of predictive modelling becomes even
stronger as we face more complicated and diverse technological choices for
larger-scale integration. High process variability not only affects the circuit
performance but also reduces manufacturing yield. To improve manufacturing yield of technologies 45 nm and below, performance variability should
be considered during the design phase. In the conventional design approach,
high variability leads to overdesigning, thereby increasing area and power
consumption. To avoid overdesigning, accurate estimation of variability is
required.
According to the International Technology Roadmap for Semiconductors
(ITRS), for technology nodes beyond 45 nm, larger amounts of process variations are expected. The increased variations are primarily due to random
dopant fluctuations, line-edge roughness, and oxide thickness fluctuation.
These variations greatly impact all aspects of circuit performance and pose
a great challenge to future integrated circuit (IC) design. To improve robustness, efficient methodology is required that considers the effect of variations
in the design flow. What matters is not only the amount of variations, but
also the sensitivity to variations. At the nanoscale, the sensitivity of transistor performance on process variations becomes more significant and is critical for robust CMOS design.
This chapter covers both the modelling principles and the applications
of predictive technology modelling (PTM) and process compact modelling (PCM) in microelectronics design. We discuss the methodology for