248
Strain-Engineered MOSFETs
Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy.
A 90-nm Logic Technology Featuring Strained-Silicon, IEEE Electron Dev. Lett.,
51, 1790–1797, 2004.
7. C.-H. Liu and T.-M. Pan, Hot Carrier and Negative-Bias Temperature Instability
Reliabilities of Strained-Si MOSFETs, IEEE Trans. Electron Dev., 54, 1799–1803, 2007.
8. A. Shickova, B. Kaczer, P. Verheyen, G. Eneman, E. San Andres, M. Jurczak,
P. Absil, H. Maes, and G. Groeseneken, Negligible Effect of Process-Induced
Strain on Intrinsic NBTI Behavior, IEEE Electron Dev Lett., 28, 242–244, 2007.
9. G. K. Dalapati, S. Chattopadhyay, K. S. K. Kwa, S. H. Olsen, Y. L. Tsang, R.
Agaiby, A. G. O’Neill, P. Dobrosz, and S. J. Bull, Impact of Strained-Si Thickness
and Ge Out-Diffusion on Gate Oxide Quality for Strained-Si Surface Channel
n-MOSFETs, IEEE Trans. Electron Dev., 53, 1142–1152, 2006.
10. F. Stern and W. E. Howard, Properties of Semiconductor Surface Inversion
Layers in the Electric Quantum Limit, Phys. Rev., 163, 816–835, 1967.
11. K. Inoue and T. Matsuno, Electron Mobilities in Modulation-Doped AlxGa1xAs/GaAs and Pseudomorphic AlxGa1-xAs/InyGa1-yAs Quantum-Well
Structures, Phys. Rev. B Condens. Matter, 47, 3771–3778, 1993.
12. T. K. Maiti, S. S. Mahato, S. K. Sarkar, and C. K. Maiti, Impact of Negative
Bias Temperature Instability on Strain-Engineered p-MOSFETs, Proceedings of
International Conference on Materials for Advanced Technologies (ICMAT 2007),
Singapore, E-13-OR52, 2007.
13. K.-W. Ang, C. Wan, K.-J. Chui, C.-H. Tung, N. Balasubramanian, M.-F. Li, G.
Samudra, and Y.-C. Yeo, Hot Carrier Reliability of Strained N-MOSFET with
Lattice Mismatched Source-Drain Stressors, Proc. IRPS, 684–685, 2007.
14. T. K. Maiti, S. S. Mahato, M. K. Bera, M. Sengupta, P. Chakraborty, C. Mahata, A.
Chakraborty, and C. K. Maiti, Stress-Induced Degradation in Strain-Engineered
nMOSFETs, Proc. Int. Symp. Physical Failure Anal. Integrated Circuits (IPFA 2008),
1–3, 2008.
15. D. Lachenal, F. Monsieur, Y. Rey-Tauriac, and A. Bravaix, HCI Degradation Model
Based on the Diffusion Equation Including the MVHR Model, Microelectronic
Eng., 84, 1921–1924, 2007.
16. S. Maeda, J.-A. Choi, J.-H. Yang, Y.-S. Jin, S.-K. Bae, Y.-W. Kim, and K.-P. Suh,
Negative Bias Temperature Instability in Triple Gate Transistors, Proc. IRPS,
8–12, 2004.
17. A. Shickova, Bias Temperature Instability Effects in Devices with Fully-Silicided
Gate Stacks, Strained-Si and Multiple-Gate Architectures, PhD thesis, Katholieke
Universiteit Leuven, 2008.
18. A. Shickova, N. Collaert, R. Rooyackers, A. De Keersgieter, T. Kauerauf, M.
Jurczak, B. Kaczer, and G. Groeseneken, Dielectric Breakdown Study of MultiGate Devices, Proc. ULIS, 141–144, 2006.
19. A. Shickova, P. Verheyen, G. Eneman, R. Degraeve, E. Simoen, P. Favia, D.
O. Klenov, E. S. Andrés, B. Kaczer, M. Jurczak, P. Absil, H. E. Maes, and G.
Groeseneken, Reliability of Strained-Si Devices with Post-Oxide-Deposition
Strain Introduction, IEEE Trans. Electron Dev., 55, 3432–3441, 2008.
Strain-Engineered MOSFETs
Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy.
A 90-nm Logic Technology Featuring Strained-Silicon, IEEE Electron Dev. Lett.,
51, 1790–1797, 2004.
7. C.-H. Liu and T.-M. Pan, Hot Carrier and Negative-Bias Temperature Instability
Reliabilities of Strained-Si MOSFETs, IEEE Trans. Electron Dev., 54, 1799–1803, 2007.
8. A. Shickova, B. Kaczer, P. Verheyen, G. Eneman, E. San Andres, M. Jurczak,
P. Absil, H. Maes, and G. Groeseneken, Negligible Effect of Process-Induced
Strain on Intrinsic NBTI Behavior, IEEE Electron Dev Lett., 28, 242–244, 2007.
9. G. K. Dalapati, S. Chattopadhyay, K. S. K. Kwa, S. H. Olsen, Y. L. Tsang, R.
Agaiby, A. G. O’Neill, P. Dobrosz, and S. J. Bull, Impact of Strained-Si Thickness
and Ge Out-Diffusion on Gate Oxide Quality for Strained-Si Surface Channel
n-MOSFETs, IEEE Trans. Electron Dev., 53, 1142–1152, 2006.
10. F. Stern and W. E. Howard, Properties of Semiconductor Surface Inversion
Layers in the Electric Quantum Limit, Phys. Rev., 163, 816–835, 1967.
11. K. Inoue and T. Matsuno, Electron Mobilities in Modulation-Doped AlxGa1xAs/GaAs and Pseudomorphic AlxGa1-xAs/InyGa1-yAs Quantum-Well
Structures, Phys. Rev. B Condens. Matter, 47, 3771–3778, 1993.
12. T. K. Maiti, S. S. Mahato, S. K. Sarkar, and C. K. Maiti, Impact of Negative
Bias Temperature Instability on Strain-Engineered p-MOSFETs, Proceedings of
International Conference on Materials for Advanced Technologies (ICMAT 2007),
Singapore, E-13-OR52, 2007.
13. K.-W. Ang, C. Wan, K.-J. Chui, C.-H. Tung, N. Balasubramanian, M.-F. Li, G.
Samudra, and Y.-C. Yeo, Hot Carrier Reliability of Strained N-MOSFET with
Lattice Mismatched Source-Drain Stressors, Proc. IRPS, 684–685, 2007.
14. T. K. Maiti, S. S. Mahato, M. K. Bera, M. Sengupta, P. Chakraborty, C. Mahata, A.
Chakraborty, and C. K. Maiti, Stress-Induced Degradation in Strain-Engineered
nMOSFETs, Proc. Int. Symp. Physical Failure Anal. Integrated Circuits (IPFA 2008),
1–3, 2008.
15. D. Lachenal, F. Monsieur, Y. Rey-Tauriac, and A. Bravaix, HCI Degradation Model
Based on the Diffusion Equation Including the MVHR Model, Microelectronic
Eng., 84, 1921–1924, 2007.
16. S. Maeda, J.-A. Choi, J.-H. Yang, Y.-S. Jin, S.-K. Bae, Y.-W. Kim, and K.-P. Suh,
Negative Bias Temperature Instability in Triple Gate Transistors, Proc. IRPS,
8–12, 2004.
17. A. Shickova, Bias Temperature Instability Effects in Devices with Fully-Silicided
Gate Stacks, Strained-Si and Multiple-Gate Architectures, PhD thesis, Katholieke
Universiteit Leuven, 2008.
18. A. Shickova, N. Collaert, R. Rooyackers, A. De Keersgieter, T. Kauerauf, M.
Jurczak, B. Kaczer, and G. Groeseneken, Dielectric Breakdown Study of MultiGate Devices, Proc. ULIS, 141–144, 2006.
19. A. Shickova, P. Verheyen, G. Eneman, R. Degraeve, E. Simoen, P. Favia, D.
O. Klenov, E. S. Andrés, B. Kaczer, M. Jurczak, P. Absil, H. E. Maes, and G.
Groeseneken, Reliability of Strained-Si Devices with Post-Oxide-Deposition
Strain Introduction, IEEE Trans. Electron Dev., 55, 3432–3441, 2008.