5
Introduction
1.2 Substrate-Induced Strain Engineering
To induce appropriate strain in the channel region of MOSFETs, various
techniques have been introduced, such as substrate-induced strain, processinduced strain, and bending-induced strain. Optimisation of channel surface
crystalline orientations for maximum carrier mobilities can also provide for a
significant improvement in CMOS performance. Biaxial tensile silicon strain
has long been known to increase electron mobility, but the strain-induced
hole mobility increase is small at high vertical electric field. Substrateinduced strain engineering has become a critical feature in CMOS technology since it enhances the drain current without further gate length scaling.
Recent progress has also demonstrated the evolution of the strained Si bulk
MOS structure, such as the strained Si on SiGe-on-insulator (SGOI) MOSFET,
and the strained Si-directly-on-insulator (SSDOI) MOSFETs. With a highly
strained Si channel or a different orientation substrate in p-MOSFETs, the
performance match between the n- and p-MOSFETs for CMOS applications
might be achieved. Alternative channel materials with mobilities higher
than silicon mobility, e.g., germanium or III-V semiconductors, can be used
for device performance enhancement.
In Chapter 2, the issue of the substrates for strained-layer SiGe applications
is addressed, followed by a short review of the present epitaxy techniques
in use for SiGe research and production. A comprehensive review on stateof-the-art substrate-induced strain engineering methodologies in CMOS
technology will be presented. Strain effect on various n- and p-channel
MOSFETs in both inversion and accumulation regions are discussed. A systematic analysis of the strain effects on deeply scaled n- and p-MOSFETs
with Si, SiGe, strained Si, strained Ge, and Ge channel is presented. Besides
strained Si on the traditional (100) plane, it may be advantageous to change
the crystal orientation to optimise CMOS circuit performance. Another way
of enhancing channel mobility without the introduction of any new channel
materials is the use of the hybrid crystal orientation technique. The carrier
mobility of inversion layers depends on surface orientation and current flow
directions, due to asymmetry of the carrier effective masses in the Si crystal
lattice. Hybrid orientation technology (HOT) will also be discussed.
1.3 Process-Induced Stress Engineering
Process-induced (local) strain was first introduced into planar Si MOSFET
transistors by Intel in 2002. Uniaxial strain is generated by local structural
change near the channel region. The embedded SiGe (e-SiGe) under the
source and drain regions resulted in larger than expected device performance
Introduction
1.2 Substrate-Induced Strain Engineering
To induce appropriate strain in the channel region of MOSFETs, various
techniques have been introduced, such as substrate-induced strain, processinduced strain, and bending-induced strain. Optimisation of channel surface
crystalline orientations for maximum carrier mobilities can also provide for a
significant improvement in CMOS performance. Biaxial tensile silicon strain
has long been known to increase electron mobility, but the strain-induced
hole mobility increase is small at high vertical electric field. Substrateinduced strain engineering has become a critical feature in CMOS technology since it enhances the drain current without further gate length scaling.
Recent progress has also demonstrated the evolution of the strained Si bulk
MOS structure, such as the strained Si on SiGe-on-insulator (SGOI) MOSFET,
and the strained Si-directly-on-insulator (SSDOI) MOSFETs. With a highly
strained Si channel or a different orientation substrate in p-MOSFETs, the
performance match between the n- and p-MOSFETs for CMOS applications
might be achieved. Alternative channel materials with mobilities higher
than silicon mobility, e.g., germanium or III-V semiconductors, can be used
for device performance enhancement.
In Chapter 2, the issue of the substrates for strained-layer SiGe applications
is addressed, followed by a short review of the present epitaxy techniques
in use for SiGe research and production. A comprehensive review on stateof-the-art substrate-induced strain engineering methodologies in CMOS
technology will be presented. Strain effect on various n- and p-channel
MOSFETs in both inversion and accumulation regions are discussed. A systematic analysis of the strain effects on deeply scaled n- and p-MOSFETs
with Si, SiGe, strained Si, strained Ge, and Ge channel is presented. Besides
strained Si on the traditional (100) plane, it may be advantageous to change
the crystal orientation to optimise CMOS circuit performance. Another way
of enhancing channel mobility without the introduction of any new channel
materials is the use of the hybrid crystal orientation technique. The carrier
mobility of inversion layers depends on surface orientation and current flow
directions, due to asymmetry of the carrier effective masses in the Si crystal
lattice. Hybrid orientation technology (HOT) will also be discussed.
1.3 Process-Induced Stress Engineering
Process-induced (local) strain was first introduced into planar Si MOSFET
transistors by Intel in 2002. Uniaxial strain is generated by local structural
change near the channel region. The embedded SiGe (e-SiGe) under the
source and drain regions resulted in larger than expected device performance