6
Strain-Engineered MOSFETs
enhancement, which is attributed to compressive channel. The strain is
induced by the lattice mismatch between Si and SiGe. Owing to the relative
ease of integrating process-induced strain modules in conventional CMOS
processing, strain-enhanced scaling is now possible. However, uniaxial channel stress requires different stress types (compressive and tensile for n- and
p-MOSFETs, respectively). Stress development in integrated circuits may
occur at any stage of the manufacturing process from a variety of sources that
affect the device performance. Several standard processing steps can be used
to introduce uniaxial strain in silicon channel for MOSFET strain engineering. Various techniques have been proposed to incorporate strain in the channel region. Most successful among these has been the introduction of SiGe
in the source/drain regions, use of tensile and compressive liners, as well as
the stress memorisation technique. The two critical areas of stress development in integrated circuits are (1) front-end-of-line strain-engineered channel
for increasing carrier mobility and (2) thermomechanical stress development
near Cu through-silicon vias (TSVs) for 3D integration. A clear understanding of the evolution of stress/strain in integrated circuits and novel ways in
which it can be characterised can lead to more effective strategies to mitigate or control the stress development. Equivalent scaling strategies such as
strain-engineered MOSFET channels and 3D integration schemes are important for maintaining integrated circuits performance enhancement in future
semiconductor technology nodes.
In Chapter 3, typical uniaxial technologies, such as embedded or raised SiGe
or SiC source/drains, Ge preamorphisation source/drain extension technology, the stress memorisation technique, and tensile or comprehensive capping
layers, stress liners, and contact etch stop layers, are discussed in detail. The
importance of global and local strain techniques is outlined. Layout-dependent
compact modelling of mobility, velocity, and threshold voltage in strain-engineered state-of-the-art transistors using e-SiGe, dual-stress liner, and shallow
trench isolation stresses are discussed. Three-dimensional integration has
emerged as a viable solution to achieve higher packing density. Toward 3D
integration, through-silicon vias, which directly connect stacked structures
die to die, are being employed. It is important to note that the through-silicon
vias (TSVs) generate a stress-induced thermal mismatch between TSVs and the
silicon bulk, which affects the performance of nearby transistors, diodes, and
associated circuits. Thus it is important to study the impact of TSV-induced
stress on device and circuit performance. TSVs also interact with polysilicon
and shallow trench isolation layout pattern density. A summary of benefits of
3D integrated circuit (ICs) and key process steps involved in their fabrication,
particularly relating to through-silicon vias, will be discussed. In nanometerscale CMOS transistors performance variability is common and layout-dependent effects have become important. The important issues of device/circuit
interactions for the 22 nm node will include discussions on variability; design
for manufacturing and the impact of back-end technology elements on overall
device performance will also be covered.
Strain-Engineered MOSFETs
enhancement, which is attributed to compressive channel. The strain is
induced by the lattice mismatch between Si and SiGe. Owing to the relative
ease of integrating process-induced strain modules in conventional CMOS
processing, strain-enhanced scaling is now possible. However, uniaxial channel stress requires different stress types (compressive and tensile for n- and
p-MOSFETs, respectively). Stress development in integrated circuits may
occur at any stage of the manufacturing process from a variety of sources that
affect the device performance. Several standard processing steps can be used
to introduce uniaxial strain in silicon channel for MOSFET strain engineering. Various techniques have been proposed to incorporate strain in the channel region. Most successful among these has been the introduction of SiGe
in the source/drain regions, use of tensile and compressive liners, as well as
the stress memorisation technique. The two critical areas of stress development in integrated circuits are (1) front-end-of-line strain-engineered channel
for increasing carrier mobility and (2) thermomechanical stress development
near Cu through-silicon vias (TSVs) for 3D integration. A clear understanding of the evolution of stress/strain in integrated circuits and novel ways in
which it can be characterised can lead to more effective strategies to mitigate or control the stress development. Equivalent scaling strategies such as
strain-engineered MOSFET channels and 3D integration schemes are important for maintaining integrated circuits performance enhancement in future
semiconductor technology nodes.
In Chapter 3, typical uniaxial technologies, such as embedded or raised SiGe
or SiC source/drains, Ge preamorphisation source/drain extension technology, the stress memorisation technique, and tensile or comprehensive capping
layers, stress liners, and contact etch stop layers, are discussed in detail. The
importance of global and local strain techniques is outlined. Layout-dependent
compact modelling of mobility, velocity, and threshold voltage in strain-engineered state-of-the-art transistors using e-SiGe, dual-stress liner, and shallow
trench isolation stresses are discussed. Three-dimensional integration has
emerged as a viable solution to achieve higher packing density. Toward 3D
integration, through-silicon vias, which directly connect stacked structures
die to die, are being employed. It is important to note that the through-silicon
vias (TSVs) generate a stress-induced thermal mismatch between TSVs and the
silicon bulk, which affects the performance of nearby transistors, diodes, and
associated circuits. Thus it is important to study the impact of TSV-induced
stress on device and circuit performance. TSVs also interact with polysilicon
and shallow trench isolation layout pattern density. A summary of benefits of
3D integrated circuit (ICs) and key process steps involved in their fabrication,
particularly relating to through-silicon vias, will be discussed. In nanometerscale CMOS transistors performance variability is common and layout-dependent effects have become important. The important issues of device/circuit
interactions for the 22 nm node will include discussions on variability; design
for manufacturing and the impact of back-end technology elements on overall
device performance will also be covered.