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Strain-Engineered MOSFETs
8.5 Reliability Issues in FinFETs
Most integrated circuits are fabricated on (100)-oriented Si wafers. However,
it has been known since 1968 that hole mobility is higher for p-MOSFETs on
(110)-oriented wafers with the channel in the <110> direction. Along with
the higher hole mobility, however, the (110) Si surface has a higher Si bond
availability. This increases the probability of de-passivated Si bonds, and one
would expect more severe NBTI degradation, as indeed has been observed
[16]. This is a potential problem if (110)-oriented wafers become important.
For certain 3D devices, e.g., FinFETs, when fabricated on (100) wafers with
the channel in the conventional <110> direction, the vertical sidewalls are
(110) oriented, leading to NBTI problems. However, forming FinFETs on
(100) wafers with the channel in the <100> direction leads to (100) vertical
sidewalls. In the case of the triple-gate devices, approximately two-thirds
of the total active area is on the lateral (110) sides, whereas in the case of
planar devices almost all the active area is on the top (100)-oriented side.
(110)-oriented Si surfaces are known to have a higher density of available Si
bonds, and thus a higher density of interface states. The authors reported
that the threshold voltage shift caused by negative bias temperature stress for
triple-gate transistors was worse than that in planar devices and attributed
this effect to the larger trap density of the (110) sidewall channel. In order to
study this effect, 45° rotated notch structures, having (100) crystal orientation on both top and sidewalls, are used for comparison. Shickova [17] has
addressed the effects of additional processing steps required to introduce
strain, showing that their effects need to be considered in order to make a
valid NBTI comparison, ensuring that the compared devices are stressed at
the same E ox.
The new high-k dielectrics also contribute to the already increased threshold voltage shifts. Thus, a proper passivation of the dielectric is critical in
order to overcome these problems. Passivation by fluorine as a possible
means to reduce the number of interface and bulk defects is an attractive
alternative to hydrogen passivation, and it was the subject of several recent
studies. Another concern of the reliability of the multigate devices is the
already mentioned “corner effect,” caused by the concentration of the electric
field around the fin corners. This local increase of the electric field may lead
to preferential breakdown at the fin corners, in case an appropriate corner
rounding processing has not been used [18, 19]. A systematic and comprehensive study of the impact of process-induced strain on NBTI reliability
has been reported, including devices with different gate stacks, as well as
different strain introduction techniques. The study included devices with
different gate stacks as well as different strain introduction techniques. Gate
stacks studied include poly-Si/SiON, TiN/HfO 2 /SiO 2 , and Ni fully silicided
gates (FUSI)/HfSiON/SiO 2 . Strain introduction techniques include compressive stressor layers (contact etch stop layers (CESLs)) and SiGe S/D. Two
Strain-Engineered MOSFETs
8.5 Reliability Issues in FinFETs
Most integrated circuits are fabricated on (100)-oriented Si wafers. However,
it has been known since 1968 that hole mobility is higher for p-MOSFETs on
(110)-oriented wafers with the channel in the <110> direction. Along with
the higher hole mobility, however, the (110) Si surface has a higher Si bond
availability. This increases the probability of de-passivated Si bonds, and one
would expect more severe NBTI degradation, as indeed has been observed
[16]. This is a potential problem if (110)-oriented wafers become important.
For certain 3D devices, e.g., FinFETs, when fabricated on (100) wafers with
the channel in the conventional <110> direction, the vertical sidewalls are
(110) oriented, leading to NBTI problems. However, forming FinFETs on
(100) wafers with the channel in the <100> direction leads to (100) vertical
sidewalls. In the case of the triple-gate devices, approximately two-thirds
of the total active area is on the lateral (110) sides, whereas in the case of
planar devices almost all the active area is on the top (100)-oriented side.
(110)-oriented Si surfaces are known to have a higher density of available Si
bonds, and thus a higher density of interface states. The authors reported
that the threshold voltage shift caused by negative bias temperature stress for
triple-gate transistors was worse than that in planar devices and attributed
this effect to the larger trap density of the (110) sidewall channel. In order to
study this effect, 45° rotated notch structures, having (100) crystal orientation on both top and sidewalls, are used for comparison. Shickova [17] has
addressed the effects of additional processing steps required to introduce
strain, showing that their effects need to be considered in order to make a
valid NBTI comparison, ensuring that the compared devices are stressed at
the same E ox.
The new high-k dielectrics also contribute to the already increased threshold voltage shifts. Thus, a proper passivation of the dielectric is critical in
order to overcome these problems. Passivation by fluorine as a possible
means to reduce the number of interface and bulk defects is an attractive
alternative to hydrogen passivation, and it was the subject of several recent
studies. Another concern of the reliability of the multigate devices is the
already mentioned “corner effect,” caused by the concentration of the electric
field around the fin corners. This local increase of the electric field may lead
to preferential breakdown at the fin corners, in case an appropriate corner
rounding processing has not been used [18, 19]. A systematic and comprehensive study of the impact of process-induced strain on NBTI reliability
has been reported, including devices with different gate stacks, as well as
different strain introduction techniques. The study included devices with
different gate stacks as well as different strain introduction techniques. Gate
stacks studied include poly-Si/SiON, TiN/HfO 2 /SiO 2 , and Ni fully silicided
gates (FUSI)/HfSiON/SiO 2 . Strain introduction techniques include compressive stressor layers (contact etch stop layers (CESLs)) and SiGe S/D. Two