240
Strain-Engineered MOSFETs
10
1
10
11
Interface Trap Concentration (cm
–2
)
10
12
nMOSFET
L g = 45 nm
10
2
10
3
Time (s)
10
4
10
5
No strain
With strain
FIGURE 8.5
Trap distribution at the interface.
200
160
120
80
Drain Current (μA/μm)
40
0
0.0
0.1
0.2
0.3
0.4
Gate Bias (V)
Before electrical stress
PSS-nMOSFET
L g = 45 nm
After electrical stress
0.5
0.6
0.7
FIGURE 8.6
Simulated gate voltage vs. drain current (I ds- V gs ) characteristics for process-induced strained Si
n-MOSFETs showing device degradation. A decrease in drain current is observed.
Strain-Engineered MOSFETs
10
1
10
11
Interface Trap Concentration (cm
–2
)
10
12
nMOSFET
L g = 45 nm
10
2
10
3
Time (s)
10
4
10
5
No strain
With strain
FIGURE 8.5
Trap distribution at the interface.
200
160
120
80
Drain Current (μA/μm)
40
0
0.0
0.1
0.2
0.3
0.4
Gate Bias (V)
Before electrical stress
PSS-nMOSFET
L g = 45 nm
After electrical stress
0.5
0.6
0.7
FIGURE 8.6
Simulated gate voltage vs. drain current (I ds- V gs ) characteristics for process-induced strained Si
n-MOSFETs showing device degradation. A decrease in drain current is observed.