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Reliability and Degradation of Strain-Engineered MOSFETs
components: a permanent component that remains after stress removal and
a reversible component that recovers.
Hot-carrier injection (HCI), although almost alleviated in current generation n-MOSFETs, is another mechanism that can also create defects at the Si/
SiO 2 interface near the drain edge as well as in the oxide bulk [3]. Similar to
NBTI, the traps shift the device parameters and degrade the device performance. The damage is due to carrier heating in the high electric field near the
drain side of the MOSFET, resulting in impact ionisation and subsequent degradation. Historically, HCI has been more significant in p-MOSFETs because
electrons have higher mobilities (due to lower effective mass) than holes, and
thus can gain higher energy from the channel electric field. HCI has a faster
rate of degradation than NBTI. HCI occurs during the low-to-high transition
of the gate of an n-MOSFET; therefore, the degradation increases for high
switching activity or higher frequency of operation.
In integrated circuits, MOSFETs operate under various stress conditions at different times, and are therefore exposed to different degradation
types. For instance, in a CMOS inverter, the fundamental building block
of the digital integrated circuits (ICs), both the n-MOSFET and the p-MOSFET, are tied to the same input voltage [4]. When the input signal is low (≈
0 V), the p-MOSFET is under NBTI stress, and therefore degrades while
the n-MOSFET is turned off. When the input is pulled to high (V DD ), the
n-MOSFET goes through an impact ionisation condition and experiences
HCI degradation. At the same time, p-MOSFET is turned off and some of
the NBTI damage relaxes. Due to the fact that each degradation mechanism
generates defects either in the bulk oxide or at the interface, the overall
MOSFET degradation can be very complex.
8.1 NBTI in Strain-Engineered p-MOSFETs
State-of-the-art high-performance Si CMOS technologies rely on strain
engineering, based on either a global approach using high-mobility substrates or implementation of local stressors [5]. Semiconductor manufacturers have successfully adopted strain engineering in 45 nm technology [6].
Local strain techniques are being adopted due to their low cost and ease in
integration. Local stress may be induced by shallow trench isolation (STI),
strained SiN cap layers, silicidation, and SiGe or SiC pockets. A compressive strain is introduced in the p-MOSFET channel by using embedded SiGe
(e-SiGe) pockets in the source and drain region. Strain in the channel region
affects device parameters such as negative bias temperature instabilities,
low-frequency noise, radiation hardness, gate oxide quality, and hot-carrier
performance. Recent reports [7] indicate that strain-engineered MOSFETs
Reliability and Degradation of Strain-Engineered MOSFETs
components: a permanent component that remains after stress removal and
a reversible component that recovers.
Hot-carrier injection (HCI), although almost alleviated in current generation n-MOSFETs, is another mechanism that can also create defects at the Si/
SiO 2 interface near the drain edge as well as in the oxide bulk [3]. Similar to
NBTI, the traps shift the device parameters and degrade the device performance. The damage is due to carrier heating in the high electric field near the
drain side of the MOSFET, resulting in impact ionisation and subsequent degradation. Historically, HCI has been more significant in p-MOSFETs because
electrons have higher mobilities (due to lower effective mass) than holes, and
thus can gain higher energy from the channel electric field. HCI has a faster
rate of degradation than NBTI. HCI occurs during the low-to-high transition
of the gate of an n-MOSFET; therefore, the degradation increases for high
switching activity or higher frequency of operation.
In integrated circuits, MOSFETs operate under various stress conditions at different times, and are therefore exposed to different degradation
types. For instance, in a CMOS inverter, the fundamental building block
of the digital integrated circuits (ICs), both the n-MOSFET and the p-MOSFET, are tied to the same input voltage [4]. When the input signal is low (≈
0 V), the p-MOSFET is under NBTI stress, and therefore degrades while
the n-MOSFET is turned off. When the input is pulled to high (V DD ), the
n-MOSFET goes through an impact ionisation condition and experiences
HCI degradation. At the same time, p-MOSFET is turned off and some of
the NBTI damage relaxes. Due to the fact that each degradation mechanism
generates defects either in the bulk oxide or at the interface, the overall
MOSFET degradation can be very complex.
8.1 NBTI in Strain-Engineered p-MOSFETs
State-of-the-art high-performance Si CMOS technologies rely on strain
engineering, based on either a global approach using high-mobility substrates or implementation of local stressors [5]. Semiconductor manufacturers have successfully adopted strain engineering in 45 nm technology [6].
Local strain techniques are being adopted due to their low cost and ease in
integration. Local stress may be induced by shallow trench isolation (STI),
strained SiN cap layers, silicidation, and SiGe or SiC pockets. A compressive strain is introduced in the p-MOSFET channel by using embedded SiGe
(e-SiGe) pockets in the source and drain region. Strain in the channel region
affects device parameters such as negative bias temperature instabilities,
low-frequency noise, radiation hardness, gate oxide quality, and hot-carrier
performance. Recent reports [7] indicate that strain-engineered MOSFETs