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Strain-Engineered MOSFETs
S/D etch step. As shown in Figures 7.23 and 7.24, prior to etch, there is no
stress in the top silicon layer, and there is uniform compressive stress in the
SiGe layer. The etch step creates a lateral free surface, allowing the SiGe layer
to expand, reducing its compressive stress and transferring tensile stress into
the overlying silicon layer.
7.7 Summary
The technology CAD (TCAD)-based simulation approach, which includes
the modelling of process-induced stress for the scaling studies of strained
Si MOSFETs, is discussed in detail. Process and device simulations are performed to verify the reported experimental results for p-MOSFETs with
embedded SiGe pockets and n-MOSFETs with tensile nitride capping layers. It is shown that p-MOSFET performance can be improved significantly
when S/D regions are filled with SiGe pockets. For a given technology node,
several options exist to increase the channel stress. For p-MOSFETs, increase
of recess depth, Ge concentration, and decrease in channel length incorporate higher stress. For n-MOSFETs, increase of cap layer thickness and
decrease of gate length would generate higher stress. Very high f T values
have been obtained for process-induced strained Si MOSFETs and need to
be verified experimentally.
DC/AC performance of process-induced strained Si n- and p-MOSFETs
in hybrid orientation technology has been studied using technology CAD
tools that properly account for the physical mechanisms, such as orientationdependent and process-induced strain-dependent mobility models. We have
studied the effects of mobility enhancement, induced by surface orientation
change, and also process-induced strain, simultaneously, on the RF performance of CMOS devices. Peak f T values of about 524 and 239 GHz are predicted for n- and p-MOSFETs, respectively, in hybrid orientation technology
involving process-induced strain. Our predictive simulation results have
shown the superiority of hybrid orientation technology.
Review Questions
1. What is technology CAD?
2. What is process simulation?
3. What is device simulation?
4. What is the importance of TCAD in DFM?
Strain-Engineered MOSFETs
S/D etch step. As shown in Figures 7.23 and 7.24, prior to etch, there is no
stress in the top silicon layer, and there is uniform compressive stress in the
SiGe layer. The etch step creates a lateral free surface, allowing the SiGe layer
to expand, reducing its compressive stress and transferring tensile stress into
the overlying silicon layer.
7.7 Summary
The technology CAD (TCAD)-based simulation approach, which includes
the modelling of process-induced stress for the scaling studies of strained
Si MOSFETs, is discussed in detail. Process and device simulations are performed to verify the reported experimental results for p-MOSFETs with
embedded SiGe pockets and n-MOSFETs with tensile nitride capping layers. It is shown that p-MOSFET performance can be improved significantly
when S/D regions are filled with SiGe pockets. For a given technology node,
several options exist to increase the channel stress. For p-MOSFETs, increase
of recess depth, Ge concentration, and decrease in channel length incorporate higher stress. For n-MOSFETs, increase of cap layer thickness and
decrease of gate length would generate higher stress. Very high f T values
have been obtained for process-induced strained Si MOSFETs and need to
be verified experimentally.
DC/AC performance of process-induced strained Si n- and p-MOSFETs
in hybrid orientation technology has been studied using technology CAD
tools that properly account for the physical mechanisms, such as orientationdependent and process-induced strain-dependent mobility models. We have
studied the effects of mobility enhancement, induced by surface orientation
change, and also process-induced strain, simultaneously, on the RF performance of CMOS devices. Peak f T values of about 524 and 239 GHz are predicted for n- and p-MOSFETs, respectively, in hybrid orientation technology
involving process-induced strain. Our predictive simulation results have
shown the superiority of hybrid orientation technology.
Review Questions
1. What is technology CAD?
2. What is process simulation?
3. What is device simulation?
4. What is the importance of TCAD in DFM?