224
Strain-Engineered MOSFETs
uniaxial <110> p-MOSFETs, respectively, have been obtained. The highest f T
values for uniaxial strain n-MOSFETs in the <100> direction and p-MOSFETs
in the <110> are due to higher orientation-dependent mobility enhancement.
7.6 Simulation of Embedded SiGe MOSFETs
A new strained silicon concept that utilises elastic relaxation of a buried compressive SiGe layer to induce tensile strain in the channel has been reported [8].
The Rev. e-SiGe (reverse e-SiGe) technique has been shown to be effective,
inducing a level of stress comparable to or exceeding conventional strained
silicon techniques, and it is shown to be scalable down to a gate length of 10
nm. Donaton et al. [9] have demonstrated a substantial drive current enhancement in sub-100 nm n-MOSFETs and basic simulations of the influence of the
device parameters on the channel stress. These results were quite promising.
In the following, we present an extensive simulation study of a MOSFET with
embedded SiGe. Simulations were performed to calculate the channel stress
for device structures. For fabrication, a standard CMOS process is completed
through the STI step, and then the n-MOSFET active areas are etched to create
a small recess, and thin compressed SiGe and relaxed silicon layers are epitaxially grown on the active areas. The SiGe layer is compressively strained
because its lattice constant is larger than the lattice constant of silicon. Then,
the process is continued through a standard gate stack process, including
gate oxide growth, gate and silicon-nitride cap deposition, gate etch, extension, halo implant, and spacer definition. The source/drain areas are then
etched. This is the most important step in the process, as it creates a lateral
free surface allowing the compressed buried SiGe layer to elastically expand,
reducing the compressive stress in the SiGe and inducing tensile stress in the
silicon above. Silicon is then regrown in the recessed source/drain areas, and
the CMOS fabrication process is continued to completion.
ATHENA [10] simulation of stress in a MOSFET structure with an embedded SiGe layer is discussed below. The simulated process includes epitaxial
growth of thin compressed SiGe and relaxed silicon layers. The standard gate
stacks are then emulated by gate oxide and poly-deposition and oxide spacer
formation. All important geometrical characteristics of the test structure,
including thicknesses of different layers, spacer width, gate length, etc., are
parameterised. This allows investigation of effects of the parameter variations on important device characteristics. The simulation parameter set used
approximately corresponds to those reported for experimental MOSFETs [8].
The most important step of this simulation run is etching of the source/drain
areas because it creates free surfaces on the sides of the buried SiGe layer.
This step results in elastic expansion of the buried layer, reducing the compressive stress inside the layer and generating tensile stress in the silicon
Strain-Engineered MOSFETs
uniaxial <110> p-MOSFETs, respectively, have been obtained. The highest f T
values for uniaxial strain n-MOSFETs in the <100> direction and p-MOSFETs
in the <110> are due to higher orientation-dependent mobility enhancement.
7.6 Simulation of Embedded SiGe MOSFETs
A new strained silicon concept that utilises elastic relaxation of a buried compressive SiGe layer to induce tensile strain in the channel has been reported [8].
The Rev. e-SiGe (reverse e-SiGe) technique has been shown to be effective,
inducing a level of stress comparable to or exceeding conventional strained
silicon techniques, and it is shown to be scalable down to a gate length of 10
nm. Donaton et al. [9] have demonstrated a substantial drive current enhancement in sub-100 nm n-MOSFETs and basic simulations of the influence of the
device parameters on the channel stress. These results were quite promising.
In the following, we present an extensive simulation study of a MOSFET with
embedded SiGe. Simulations were performed to calculate the channel stress
for device structures. For fabrication, a standard CMOS process is completed
through the STI step, and then the n-MOSFET active areas are etched to create
a small recess, and thin compressed SiGe and relaxed silicon layers are epitaxially grown on the active areas. The SiGe layer is compressively strained
because its lattice constant is larger than the lattice constant of silicon. Then,
the process is continued through a standard gate stack process, including
gate oxide growth, gate and silicon-nitride cap deposition, gate etch, extension, halo implant, and spacer definition. The source/drain areas are then
etched. This is the most important step in the process, as it creates a lateral
free surface allowing the compressed buried SiGe layer to elastically expand,
reducing the compressive stress in the SiGe and inducing tensile stress in the
silicon above. Silicon is then regrown in the recessed source/drain areas, and
the CMOS fabrication process is continued to completion.
ATHENA [10] simulation of stress in a MOSFET structure with an embedded SiGe layer is discussed below. The simulated process includes epitaxial
growth of thin compressed SiGe and relaxed silicon layers. The standard gate
stacks are then emulated by gate oxide and poly-deposition and oxide spacer
formation. All important geometrical characteristics of the test structure,
including thicknesses of different layers, spacer width, gate length, etc., are
parameterised. This allows investigation of effects of the parameter variations on important device characteristics. The simulation parameter set used
approximately corresponds to those reported for experimental MOSFETs [8].
The most important step of this simulation run is etching of the source/drain
areas because it creates free surfaces on the sides of the buried SiGe layer.
This step results in elastic expansion of the buried layer, reducing the compressive stress inside the layer and generating tensile stress in the silicon