187
Noise in Strain-Engineered Devices
6.8 Noise in Silicon Nanowire Transistors (SNWTs)
Two approaches are generally used to fabricate Si NWs as well as other
semiconductor NWs: bottom-up and top-down. In the first method, NWs
are usually grown using a metallic catalyst on a separate substrate, usually
through a vapour-liquid-solid (VLS) growth mechanism. After a chemical or mechanical separation step, the NWs are harvested and transferred
to another substrate. In the top-down approach, the NWs are fabricated
using a CMOS-compatible technology, such as lithography-based patterning and etching. Unlike the bottom-up approach, where the NWs are randomly distributed, the top-down method enables accurate positioning of
the NWs across the wafer and facilitate the ultra-large-scale integration for
high-performance nanoelectronic circuits. Moreover, due to process difficulties related to the length of grown NWs, NW release, and gate etch process,
most of the VLS-grown NW transistors have omega-shaped gate (Ω-gate)
geometry and are thus not full gate-all-around. In a long-channel MOSFET,
carriers encounter various scattering mechanisms on their path toward the
drain terminal. Carrier mobility is a well-known benchmark to judge the
intrinsic performance of a long-channel MOSFET. Equation (6.1) indicates
that the injection velocity near the source determines the on-state current of
a short-channel device. State-of-the-art short-channel devices do not operate
in the fully ballistic regime (they are at roughly 60% of the ballistic limit),
and mobility is related to velocity through effective mass and ballistic ratio.
Therefore, understanding the carrier mobility is beneficial to design and
engineer new devices for future CMOS generations. The presence of significant resistive and capacitive parasitics, as well as a lack of large capacitance
3.1
3.2
3.3
3.0
2.9
I
d (nA)
2.8
2.7
0
2
4
6
Level 1
Level 2
Level 3
Level 4
Time (sec)
8
1 0
12
FIGURE 6.33
A typical multilevel RTS observed in the tri-gate FinFET.
Noise in Strain-Engineered Devices
6.8 Noise in Silicon Nanowire Transistors (SNWTs)
Two approaches are generally used to fabricate Si NWs as well as other
semiconductor NWs: bottom-up and top-down. In the first method, NWs
are usually grown using a metallic catalyst on a separate substrate, usually
through a vapour-liquid-solid (VLS) growth mechanism. After a chemical or mechanical separation step, the NWs are harvested and transferred
to another substrate. In the top-down approach, the NWs are fabricated
using a CMOS-compatible technology, such as lithography-based patterning and etching. Unlike the bottom-up approach, where the NWs are randomly distributed, the top-down method enables accurate positioning of
the NWs across the wafer and facilitate the ultra-large-scale integration for
high-performance nanoelectronic circuits. Moreover, due to process difficulties related to the length of grown NWs, NW release, and gate etch process,
most of the VLS-grown NW transistors have omega-shaped gate (Ω-gate)
geometry and are thus not full gate-all-around. In a long-channel MOSFET,
carriers encounter various scattering mechanisms on their path toward the
drain terminal. Carrier mobility is a well-known benchmark to judge the
intrinsic performance of a long-channel MOSFET. Equation (6.1) indicates
that the injection velocity near the source determines the on-state current of
a short-channel device. State-of-the-art short-channel devices do not operate
in the fully ballistic regime (they are at roughly 60% of the ballistic limit),
and mobility is related to velocity through effective mass and ballistic ratio.
Therefore, understanding the carrier mobility is beneficial to design and
engineer new devices for future CMOS generations. The presence of significant resistive and capacitive parasitics, as well as a lack of large capacitance
3.1
3.2
3.3
3.0
2.9
I
d (nA)
2.8
2.7
0
2
4
6
Level 1
Level 2
Level 3
Level 4
Time (sec)
8
1 0
12
FIGURE 6.33
A typical multilevel RTS observed in the tri-gate FinFET.