185
Noise in Strain-Engineered Devices
gate bias. This is also due to the the increase in trap densitiy with gate bias as
depicted by Equations (6.51) and (6.52). Figure 6.30 shows the drain current
noise power spectral density S ID /I D
2 as a function of drain current I D at three
different frequencies, which shows a slope of –1. This can be explained from
Equation (6.30) as S ID /I D
2 being proportional to 1/I D for drain current, and
the total charge density Q i being independent of V DS >> mkT/q. The noise
observed is thus mobility 1/f noise.
The drain current RTSs of the FinFETs observed are shown in Figure 6.31
in a time frame of 10 s at five different gate voltages, depicting an increase in
the mean low time of the current level and decrease in the mean high time.
The capture and emission times are identified on the time-domain signal,
which leads to an interesting observation. It is known that a charged trap
leads to increased resistance, thereby leading to a high level in current. Also,
with increased gate bias, the trap occupancy should increase, or the emission
time should increase. Depending on these, the high current level is identified
as capture time and the low current level as the emission time. This leads to
the identification of the active trap to be a donor trap (in the charged state
the trap is empty).
The capture and emission times of the tri-gate FinFET obtained from
Figure 6.31 are plotted against gate bias in Figure 6.32, along with the ratio
of the capture and emission times. The inset shows the ln(τ c /τ e ) plot as a
function of gate bias with a linear fit. The results from this plot are put in
Equation (6.36), and the trap depth is estimated as 0.207 nm. Figure  6.33
I D (A)
S
ID /I
D
2
(A) (Hz
–1
)
10
–12
10
–8
10
–6
Slope = –1
100 Hz
500 Hz
1 kHz
10
–4
10
–2
10
0
10
2
10
–11 10
–10 10
–9 10
–8 10
–7 10
–6 10
–5
FIGURE 6.30
Drain current noise power spectral density, S ID /I D
2 , as a function of drain current, I D , at three
different frequencies, which shows a slope of –1.