144
Strain-Engineered MOSFETs
choice of high C G requires a thinner dielectric, which can increase direct tunneling, which enhances the leakage and increases the power consumption.
From the electrostatics point of view, high substrate doping is required for
aggressively scaled planar devices to control the short-channel effects. The
high doping results in increased junction and gate-induced drain lowering
(GIDL) degraded on current due to the increased Coulombic scattering and
increased variation in threshold voltage. In addition, extension and halo
implants needed to control short-channel effects increase source/drain parasitic series resistance, which degrades the current drive. Considering the
trade-off between the current drive, short-channel effects, and power consumption, conventional Si MOSFETs fail to satisfy the device requirements
that call for new materials and device architectures for future CMOS generations. To enhance the current drive, new channel materials such as strained
Si, SiC, SiGe, Ge, and III-V have been extensively investigated over the past
20 years. Uniaxially strained Si technology with tensile liner and embedded
SiGe stressors was incorporated into mainstream CMOS production starting at the 90 nm technology node. To further continue scaling and improve
the current drive high-permittivity-dielectric (high-κ)/metal gate technology has also been commercialised by Intel in the 45 nm technology node.
This has been shown to dramatically improve the gate leakage and power
consumption for both n- and p-MOSFET devices. Ultra-thin-body and multigate SOI devices have been shown to provide excellent scalability and immunity to short-channel effects. The geometry enables excellent electrostatic
control by the gate, and the lightly doped Si channel dramatically reduces
the random dopant fluctuation and V th variation. In addition, these device
architectures benefit from lower capacitive parasitic and junction leakage
due to the presence of a thick buried oxide. Among various options for multigate device architecture, such as double-gate, tri-gate, etc., the nanowire
(NW) channel with a wraparound gate, so called gate-all-around (GAA),
has the largest advantage in terms of electrostatic integrity. However, several undesired effects become prominent from the miniaturisation of the
device dimensions. One such unwanted effect is a strong increase of the lowfrequency noise generated in the transistor as the size of the device decreases.
Moreover, there are many unexplored issues regarding the introduction of
new materials in complementary metal-oxide-semiconductor (CMOS) technology. Therefore, electrical evaluations of devices using new materials and
architectures are highly desired.
Noise is a fundamental problem in science and engineering, recognised for
a variety of fields such as telecommunication, nanoelectronics, and biological
systems. The noise cannot be completely eliminated, and with small signal
strength, the accuracy and measurements are limited in electronic circuits.
The low-frequency noise, or 1/f noise, is the excess noise at low frequencies
whose power spectral density (PSD) approximately depends inversely on the
frequency, and therefore escalates at low frequencies. The 1/f noise originating from the transistors is a severe obstacle in analogue circuits. The 1/f noise
Strain-Engineered MOSFETs
choice of high C G requires a thinner dielectric, which can increase direct tunneling, which enhances the leakage and increases the power consumption.
From the electrostatics point of view, high substrate doping is required for
aggressively scaled planar devices to control the short-channel effects. The
high doping results in increased junction and gate-induced drain lowering
(GIDL) degraded on current due to the increased Coulombic scattering and
increased variation in threshold voltage. In addition, extension and halo
implants needed to control short-channel effects increase source/drain parasitic series resistance, which degrades the current drive. Considering the
trade-off between the current drive, short-channel effects, and power consumption, conventional Si MOSFETs fail to satisfy the device requirements
that call for new materials and device architectures for future CMOS generations. To enhance the current drive, new channel materials such as strained
Si, SiC, SiGe, Ge, and III-V have been extensively investigated over the past
20 years. Uniaxially strained Si technology with tensile liner and embedded
SiGe stressors was incorporated into mainstream CMOS production starting at the 90 nm technology node. To further continue scaling and improve
the current drive high-permittivity-dielectric (high-κ)/metal gate technology has also been commercialised by Intel in the 45 nm technology node.
This has been shown to dramatically improve the gate leakage and power
consumption for both n- and p-MOSFET devices. Ultra-thin-body and multigate SOI devices have been shown to provide excellent scalability and immunity to short-channel effects. The geometry enables excellent electrostatic
control by the gate, and the lightly doped Si channel dramatically reduces
the random dopant fluctuation and V th variation. In addition, these device
architectures benefit from lower capacitive parasitic and junction leakage
due to the presence of a thick buried oxide. Among various options for multigate device architecture, such as double-gate, tri-gate, etc., the nanowire
(NW) channel with a wraparound gate, so called gate-all-around (GAA),
has the largest advantage in terms of electrostatic integrity. However, several undesired effects become prominent from the miniaturisation of the
device dimensions. One such unwanted effect is a strong increase of the lowfrequency noise generated in the transistor as the size of the device decreases.
Moreover, there are many unexplored issues regarding the introduction of
new materials in complementary metal-oxide-semiconductor (CMOS) technology. Therefore, electrical evaluations of devices using new materials and
architectures are highly desired.
Noise is a fundamental problem in science and engineering, recognised for
a variety of fields such as telecommunication, nanoelectronics, and biological
systems. The noise cannot be completely eliminated, and with small signal
strength, the accuracy and measurements are limited in electronic circuits.
The low-frequency noise, or 1/f noise, is the excess noise at low frequencies
whose power spectral density (PSD) approximately depends inversely on the
frequency, and therefore escalates at low frequencies. The 1/f noise originating from the transistors is a severe obstacle in analogue circuits. The 1/f noise