142
Strain-Engineered MOSFETs
3. J.-P. Colinge, Ed., FinFETs and Other Multi-Gate Transistors, Springer Science +
Business Media, LLC, New York, USA, 2008.
4. L. Chang, M. Ieong, and M. Yang, CMOS Circuit Performance Enhancement by
Surface Orientation Optimization, IEEE Trans. Electron Dev., 51, 1621–1627, 2004.
5. A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. De
Meyer, Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs, IEEE
Trans. Electron Dev., 52, 1132–1140, 2005.
6. T. K. Ming, Strain Engineering for Advanced Transistor Structure, PhD thesis,
National University of Singapore, 2008.
7. H. Irie, K. Kita, K. Kyuno, and A. Toriumi, In-Plane Mobility Anisotropy and
Universality under Uni-Axial Strains in n and p-MOS Inversion Layers on (100),
[110], and (111) Si, IEEE IEDM Tech. Dig., 225–228, 2004.
8. T. Sato, Y. Takeishi, H. Hara, and Y. Okamoto, Mobility Anisotropy of Electrons
in Inversion Layers on Oxidized Silicon Surfaces, Phys. Rev. B, 4, 1950–1960, 1971.
9. K. Shin, C. O. Chui, and T.-J. King, Dual Stress Capping Layer Enhancement
Study for Hybrid Orientation finFET CMOS Technology, IEEE IEDM Tech. Dig.,
988–991, 2005.
10. G. Sun, Strain Effects on Hole Mobility of Silicon and Germanium p-Type
Metal-Oxide-Semiconductor Field-Effect-Transistors, PhD thesis, University of
Florida, 2007.
11. K. Ota, K. Sugihara, H. Sayama, T. Uchida, H. Oda, T. Eimori, H. Morimoto,
and Y. Inoue, Novel Locally Strained Channel Technique for High Performance
55nm CMOS, IEEE IEDM Tech. Dig., 27–30, 2002.
12. V. Moroz, G. Eneman, P. Verheyen, F. Nouri, L. Washington, L. Smith, M.
Jurczakl, D. Pramanik, and X. Xu, The Impact of Layout on Stress Enhanced
Transistor Performance, Proc. SISPAD, 143–146, 2005.
13. C.-C. Wang, Predictive Modelling for Extremely Scaled CMOS and Post Silicon
Devices, PhD thesis, Arizona State University, 2011.
14. F. Nouri, P. Verheyen, L. Washington, V. Moroz, I. De Wolf, M. Kawaguchi, S.
Biesemans, R. Schreutelkamp, Y. Kim, M. Shen, X. Xu, R. Rooyackers, M. Jurczak,
G. Eneman, K. De Meyer, L. Smith, D. Pramanik, H. Forstner, S. Thirupapuliyur,
and G. S. Higashi, A Systematic Study of Trade-Offs in Engineering a Locally
Strained pMOSFET, IEEE IEDM Tech. Dig., 1055–1058, 2004.
15. S. Eneman, P. Verheyen, R. Rooyackers, F. Nouri, L. Washington, R. Degraeve, B.
Kaczer, V. Moroz, A. De Keersgieter, R. Schreutelkamp, M. Kawaguchi, Y. Kim,
A. Samoilov, L. Smith, P. P. Absil, K. De Meyer, M. Jurczak, and S. Biesemans,
Layout Impact on the Performance of a Locally Strained PMOSFET, Proc. Symp.
VLSI Technol., 22–23, 2005.
16. E. Morifuji, H. Aikawa, H. Yoshimura, A. Sakata, M. Ohta, M. Iwai, and F.
Matsuoka, Layout Dependence Modelling for 45-nm CMOS with StressEnhanced Technique, IEEE Trans. Electron Dev., 56, 1991–1998, 2009.
17. V. Joshi, B. Cline, D. Sylvester, D. Blaauw, and K. Agarwal, Leakage Power
Reduction Using Stress-Enhanced Layouts, Proc. DAC, 912–917, 2008.
18. M. V. Dunga, C.-H. Lin, X. Xi, D. D. Lu, A. M. Niknejad, and C. Hu, Modelling
Advanced FET Technology in a Compact Model, IEEE Trans. Electron Dev., 53,
1971–1978, 2006.
Strain-Engineered MOSFETs
3. J.-P. Colinge, Ed., FinFETs and Other Multi-Gate Transistors, Springer Science +
Business Media, LLC, New York, USA, 2008.
4. L. Chang, M. Ieong, and M. Yang, CMOS Circuit Performance Enhancement by
Surface Orientation Optimization, IEEE Trans. Electron Dev., 51, 1621–1627, 2004.
5. A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. De
Meyer, Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs, IEEE
Trans. Electron Dev., 52, 1132–1140, 2005.
6. T. K. Ming, Strain Engineering for Advanced Transistor Structure, PhD thesis,
National University of Singapore, 2008.
7. H. Irie, K. Kita, K. Kyuno, and A. Toriumi, In-Plane Mobility Anisotropy and
Universality under Uni-Axial Strains in n and p-MOS Inversion Layers on (100),
[110], and (111) Si, IEEE IEDM Tech. Dig., 225–228, 2004.
8. T. Sato, Y. Takeishi, H. Hara, and Y. Okamoto, Mobility Anisotropy of Electrons
in Inversion Layers on Oxidized Silicon Surfaces, Phys. Rev. B, 4, 1950–1960, 1971.
9. K. Shin, C. O. Chui, and T.-J. King, Dual Stress Capping Layer Enhancement
Study for Hybrid Orientation finFET CMOS Technology, IEEE IEDM Tech. Dig.,
988–991, 2005.
10. G. Sun, Strain Effects on Hole Mobility of Silicon and Germanium p-Type
Metal-Oxide-Semiconductor Field-Effect-Transistors, PhD thesis, University of
Florida, 2007.
11. K. Ota, K. Sugihara, H. Sayama, T. Uchida, H. Oda, T. Eimori, H. Morimoto,
and Y. Inoue, Novel Locally Strained Channel Technique for High Performance
55nm CMOS, IEEE IEDM Tech. Dig., 27–30, 2002.
12. V. Moroz, G. Eneman, P. Verheyen, F. Nouri, L. Washington, L. Smith, M.
Jurczakl, D. Pramanik, and X. Xu, The Impact of Layout on Stress Enhanced
Transistor Performance, Proc. SISPAD, 143–146, 2005.
13. C.-C. Wang, Predictive Modelling for Extremely Scaled CMOS and Post Silicon
Devices, PhD thesis, Arizona State University, 2011.
14. F. Nouri, P. Verheyen, L. Washington, V. Moroz, I. De Wolf, M. Kawaguchi, S.
Biesemans, R. Schreutelkamp, Y. Kim, M. Shen, X. Xu, R. Rooyackers, M. Jurczak,
G. Eneman, K. De Meyer, L. Smith, D. Pramanik, H. Forstner, S. Thirupapuliyur,
and G. S. Higashi, A Systematic Study of Trade-Offs in Engineering a Locally
Strained pMOSFET, IEEE IEDM Tech. Dig., 1055–1058, 2004.
15. S. Eneman, P. Verheyen, R. Rooyackers, F. Nouri, L. Washington, R. Degraeve, B.
Kaczer, V. Moroz, A. De Keersgieter, R. Schreutelkamp, M. Kawaguchi, Y. Kim,
A. Samoilov, L. Smith, P. P. Absil, K. De Meyer, M. Jurczak, and S. Biesemans,
Layout Impact on the Performance of a Locally Strained PMOSFET, Proc. Symp.
VLSI Technol., 22–23, 2005.
16. E. Morifuji, H. Aikawa, H. Yoshimura, A. Sakata, M. Ohta, M. Iwai, and F.
Matsuoka, Layout Dependence Modelling for 45-nm CMOS with StressEnhanced Technique, IEEE Trans. Electron Dev., 56, 1991–1998, 2009.
17. V. Joshi, B. Cline, D. Sylvester, D. Blaauw, and K. Agarwal, Leakage Power
Reduction Using Stress-Enhanced Layouts, Proc. DAC, 912–917, 2008.
18. M. V. Dunga, C.-H. Lin, X. Xi, D. D. Lu, A. M. Niknejad, and C. Hu, Modelling
Advanced FET Technology in a Compact Model, IEEE Trans. Electron Dev., 53,
1971–1978, 2006.