141
Strain-Engineered MOSFETs
5.9 Summary
Process integration issues such as power consumption, leakage current, metal
gate electrodes, and high-k gate dielectrics have been discussed. Different
types of multigate devices in terms of their architectures were reviewed. The
tri-gate devices have been the focus of this chapter, because they are a good
compromise between processing complexity and electrical performance.
Although the GAA and the Π-gate structures show better electrical properties, they require more complex and costly processing to be implemented.
Layout dependence of strain-enhanced MOSFETs and interaction between
layout and circuit performance have been discussed. The stress dependence
provides circuit designers an alternative to optimise the circuit performance
via stress-aware layout design.
Review Questions
1. Uniaxial process-induced strain for mobility enhancement started at
the 90 nm CMOS technology node. (True/False)
2. Epitaxial SiGe S/D (e-SiGe) is used for p-MOSFET performance
enhancement. (True/False)
3. SiN capping layers are used for p-MOSFET performance enhancement. (True/False)
4. What are the advantages of high-k gate dielectrics?
5. What are the advantages of metal gate electrodes?
6. What are the disadvantages of polysilicon gate?
7. Strained SiGe induced large lateral compression in channels, resulting in higher mobility. (True/False).
8. SiGe S/D improves parasitic resistance by reducing salicide interface
resistance. (True/False)
9. Double-gate MOSFETs have lower short-channel effects. (True/False)
10. Tri-gate FinFETs are at the core of the 22 nm technology node.
(True/False)
References
1. International Technology Roadmap for Semiconductors (ITRS). http://public.
itrs.net/.
2. H. Iwai, CMOS Scaling toward sub-10nm Regime, Proc. Int. Symp. Electron
Device Microwave Optoelectronic Appl., 30–34, 2003.
Strain-Engineered MOSFETs
5.9 Summary
Process integration issues such as power consumption, leakage current, metal
gate electrodes, and high-k gate dielectrics have been discussed. Different
types of multigate devices in terms of their architectures were reviewed. The
tri-gate devices have been the focus of this chapter, because they are a good
compromise between processing complexity and electrical performance.
Although the GAA and the Π-gate structures show better electrical properties, they require more complex and costly processing to be implemented.
Layout dependence of strain-enhanced MOSFETs and interaction between
layout and circuit performance have been discussed. The stress dependence
provides circuit designers an alternative to optimise the circuit performance
via stress-aware layout design.
Review Questions
1. Uniaxial process-induced strain for mobility enhancement started at
the 90 nm CMOS technology node. (True/False)
2. Epitaxial SiGe S/D (e-SiGe) is used for p-MOSFET performance
enhancement. (True/False)
3. SiN capping layers are used for p-MOSFET performance enhancement. (True/False)
4. What are the advantages of high-k gate dielectrics?
5. What are the advantages of metal gate electrodes?
6. What are the disadvantages of polysilicon gate?
7. Strained SiGe induced large lateral compression in channels, resulting in higher mobility. (True/False).
8. SiGe S/D improves parasitic resistance by reducing salicide interface
resistance. (True/False)
9. Double-gate MOSFETs have lower short-channel effects. (True/False)
10. Tri-gate FinFETs are at the core of the 22 nm technology node.
(True/False)
References
1. International Technology Roadmap for Semiconductors (ITRS). http://public.
itrs.net/.
2. H. Iwai, CMOS Scaling toward sub-10nm Regime, Proc. Int. Symp. Electron
Device Microwave Optoelectronic Appl., 30–34, 2003.