139
Strain-Engineered MOSFETs
depends on both the applied stress magnitude and circuit layout parameters,
such as gate length, source/drain size, and the distance from gate edge to STI
because of the nature of mechanical stress in silicon: nonuniform distribution. DSL introduces the stress by depositing a highly stressed silicon nitride
layer, tensile stress for the n-MOSFET region, and compressive stress for the
p-MOSFET region, over the entire wafer to elevate carrier mobility. In SMT, the
stress in the channel is transferred from the stressed deposited dielectric and is
memorised during the recrystallisation of the active area and poly-gate when
thermal annealing is activated. STI stress results from the difference in thermal expansion coefficients between SiO 2 and Si. It is an intrinsic stress source
and not intentionally built up for enhancing device performance enhancement. Process-induced stress has been effectively applied for the 90 nm node
and beyond. Since the stress is nonuniformly distributed in the channel, the
enhancement in carrier mobility, velocity, and threshold voltage shift strongly
depend on circuit layout, leading to systematic performance variations among
transistors. However, special layout engineering is required for practical
application because process-induced strain is localised strain and depends
on the physical dimensions of the transistor, such as gate length and channel
width [14, 15], as well as the surrounding structures. It is important to understand the degree to which the distributions of device parameter (for example,
gate length) values of neighbouring, near-neighbouring, and well-separated
devices are related to each other (as a function of physical separation).
Layout dependences for stress-enhanced MOSFETs, including contact
positioning, the second neighbouring polyeffect, and bent diffusion modeled
in 45 nm CMOS logic technology, have been reported [16]. It has been shown
that stress effect might be more serious for p-MOSFETs than for n-MOSFETs.
Figure 5.19 illustrates the TCAD simulation of stress distribution in a 45 nm
standard cell under restrictive design rules, where SiGe with 25% Ge composition is embedded in the S/D area. The stress level is widely different across
the cell, depending on transistor size and layout pitch. Such nonuniformity
results in pronounced variations among transistors as well as circuit performance, and further increases the complexity in modelling and simulation. The stress effect is weakened by shrinking the pitch of gates. The stress
modulation of embedded SiGe depends on the effective area size of SiGe, and
therefore the space of a gate and the shape of diffusion influence the performance of MOSFETs. Additionally, the well proximity effect and round shape
of patterns in lithography affect the MOSFET performance. For example, the
strain-induced threshold voltage shift is mainly dominated by the bottom
stress level in the channel, while the entire channel stresses are required to
be taken into consideration for the enhancement of mobility. These effects
cause the variability of devices in the cells and circuits with random patterns
as the feature size is scaled down to 45 nm CMOS logic technology.
Joshi et al. [17] have reported that the trend of the STI stress effect is attributed to the nonuniform stress distribution in the channel, but it does not
quantitatively explain how this distribution impacts the electrical properties.
Strain-Engineered MOSFETs
depends on both the applied stress magnitude and circuit layout parameters,
such as gate length, source/drain size, and the distance from gate edge to STI
because of the nature of mechanical stress in silicon: nonuniform distribution. DSL introduces the stress by depositing a highly stressed silicon nitride
layer, tensile stress for the n-MOSFET region, and compressive stress for the
p-MOSFET region, over the entire wafer to elevate carrier mobility. In SMT, the
stress in the channel is transferred from the stressed deposited dielectric and is
memorised during the recrystallisation of the active area and poly-gate when
thermal annealing is activated. STI stress results from the difference in thermal expansion coefficients between SiO 2 and Si. It is an intrinsic stress source
and not intentionally built up for enhancing device performance enhancement. Process-induced stress has been effectively applied for the 90 nm node
and beyond. Since the stress is nonuniformly distributed in the channel, the
enhancement in carrier mobility, velocity, and threshold voltage shift strongly
depend on circuit layout, leading to systematic performance variations among
transistors. However, special layout engineering is required for practical
application because process-induced strain is localised strain and depends
on the physical dimensions of the transistor, such as gate length and channel
width [14, 15], as well as the surrounding structures. It is important to understand the degree to which the distributions of device parameter (for example,
gate length) values of neighbouring, near-neighbouring, and well-separated
devices are related to each other (as a function of physical separation).
Layout dependences for stress-enhanced MOSFETs, including contact
positioning, the second neighbouring polyeffect, and bent diffusion modeled
in 45 nm CMOS logic technology, have been reported [16]. It has been shown
that stress effect might be more serious for p-MOSFETs than for n-MOSFETs.
Figure 5.19 illustrates the TCAD simulation of stress distribution in a 45 nm
standard cell under restrictive design rules, where SiGe with 25% Ge composition is embedded in the S/D area. The stress level is widely different across
the cell, depending on transistor size and layout pitch. Such nonuniformity
results in pronounced variations among transistors as well as circuit performance, and further increases the complexity in modelling and simulation. The stress effect is weakened by shrinking the pitch of gates. The stress
modulation of embedded SiGe depends on the effective area size of SiGe, and
therefore the space of a gate and the shape of diffusion influence the performance of MOSFETs. Additionally, the well proximity effect and round shape
of patterns in lithography affect the MOSFET performance. For example, the
strain-induced threshold voltage shift is mainly dominated by the bottom
stress level in the channel, while the entire channel stresses are required to
be taken into consideration for the enhancement of mobility. These effects
cause the variability of devices in the cells and circuits with random patterns
as the feature size is scaled down to 45 nm CMOS logic technology.
Joshi et al. [17] have reported that the trend of the STI stress effect is attributed to the nonuniform stress distribution in the channel, but it does not
quantitatively explain how this distribution impacts the electrical properties.