138
Strain-Engineered MOSFETs
5.8 Layout Dependence
The layout-dependent stress effect is first observed and reported from shallow trench isolation (STI) stress [11]. The insertion and placement of active
areas are optimised by STI stress to improve the circuit performance [12].
The stress profile is sensitive to the primary layout parameters, such as
channel length and source/drain diffusion length. STI width effect has been
investigated and shown to enhance circuit performance. A stress-aware layout design has been proposed to reduce leakage power. Layout-dependent
stress effects are also being observed in the state-of-the-art strain technologies. The stress dependence provides circuit designers another alternative
to optimise the circuit performance. Thus, interaction between layout and
circuit performance needs to be accurately predicted using stress models.
Toward this, the traditional efforts resort to TCAD simulation to extract the
stress level from the entire layout and analyse performance enhancement.
Compact models that capture the dependence on primary layout parameters, temperature, and other device characteristics, such as mobility, velocity,
and threshold voltage in state-of-the-art strain technologies like e-SiGe and
DSL stress techniques, have been reported [13].
The main techniques to introduce uniaxial stress include embedded SiGe
technology (e-SiGe), dual-stress liner (DSL), stress memorisation technique
(SMT), and the parasitic stress from shallow trench isolation (STI). Embedded
SiGe technology embeds SiGe in the source and drain area to introduce compressive stress for p-MOSFETs. The amount of performance enhancement
4
3
2
Mobility Enhancement Factor ∆µ/µ
1
0
0
1
Uniaxial Compressive Stress/GPa
2
SG (110)/<110>
SG (001)/<110>
FinFETs (110)/<110>
p inv = 1×10
13 /cm
2
3
FIGURE 5.18
Hole mobility enhancement factor of FinFETs under uniaxial compressive stress at charge
density of 1 × 10 13 /cm 2 . (After Sun, G., Strain Effects on Hole Mobility of Silicon and
Germanium p-Type Metal-Oxide-Semiconductor Field-Effect-Transistors, PhD thesis,
University of Florida, 2007.)
Strain-Engineered MOSFETs
5.8 Layout Dependence
The layout-dependent stress effect is first observed and reported from shallow trench isolation (STI) stress [11]. The insertion and placement of active
areas are optimised by STI stress to improve the circuit performance [12].
The stress profile is sensitive to the primary layout parameters, such as
channel length and source/drain diffusion length. STI width effect has been
investigated and shown to enhance circuit performance. A stress-aware layout design has been proposed to reduce leakage power. Layout-dependent
stress effects are also being observed in the state-of-the-art strain technologies. The stress dependence provides circuit designers another alternative
to optimise the circuit performance. Thus, interaction between layout and
circuit performance needs to be accurately predicted using stress models.
Toward this, the traditional efforts resort to TCAD simulation to extract the
stress level from the entire layout and analyse performance enhancement.
Compact models that capture the dependence on primary layout parameters, temperature, and other device characteristics, such as mobility, velocity,
and threshold voltage in state-of-the-art strain technologies like e-SiGe and
DSL stress techniques, have been reported [13].
The main techniques to introduce uniaxial stress include embedded SiGe
technology (e-SiGe), dual-stress liner (DSL), stress memorisation technique
(SMT), and the parasitic stress from shallow trench isolation (STI). Embedded
SiGe technology embeds SiGe in the source and drain area to introduce compressive stress for p-MOSFETs. The amount of performance enhancement
4
3
2
Mobility Enhancement Factor ∆µ/µ
1
0
0
1
Uniaxial Compressive Stress/GPa
2
SG (110)/<110>
SG (001)/<110>
FinFETs (110)/<110>
p inv = 1×10
13 /cm
2
3
FIGURE 5.18
Hole mobility enhancement factor of FinFETs under uniaxial compressive stress at charge
density of 1 × 10 13 /cm 2 . (After Sun, G., Strain Effects on Hole Mobility of Silicon and
Germanium p-Type Metal-Oxide-Semiconductor Field-Effect-Transistors, PhD thesis,
University of Florida, 2007.)