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Strain-Engineered MOSFETs
and (110) side surfaces sitting on top of the buried oxide (BOX). A simplified process flow includes the active region, gate, contact, and metal
level patterning. The spacer, implant, and silicide process modules are
all self-aligned, as in standard planar CMOS processing. Tri-gate FinFET
devices have the following advantages: provide more drive current, work
in three dimensions, have a geometry advantage, and are fully depleted.
A high-performance tri-gate fully depleted CMOS with 60 nm physical
gate lengths has been demonstrated that exhibits lower leakage than a
standard planar CMOS.
Among the various approaches, introduction of stress by metal-nitride
gate is promising. It has been reported that fully silicided metal gate can
induce strain in the transistor channel, and the localised strain could be
exploited to enhance the performance of aggressively scaled transistors.
FinFET structures allow the use of low-channel dopant concentration, and
avoid problems associated with random dopant fluctuation. The threshold
voltage of FinFETs can be set through gate work function engineering
using metal gates, which additionally eliminate the gate depletion effect
and dopant penetration problem for improved drive current. For n-channel
FinFET devices, the optimal gate work function lies between the midgap
and the conduction band of Si, which necessitates the use of metal gates. A
simple and cost-effective technique used to incorporate strain in the channel region of FinFET devices has been reported [6]. It is shown that the
metal gate can affect the transistor performance through the stress developed during the fabrication process. However, gate work function tuning,
process integration, and compatibility with gate dielectric continue to be
the major challenges in metal gate technology development. Annealing
of a TaN gate electrode capped with a SiN layer leads to the exertion of
a compressive stress on the Si fin. This results in a significant enhancement of the drive current in n-channel FinFETs. Mesa-isolated n-channel
FinFETs with TaN gates were fabricated on SOI with a (001) surface and
45 nm thick Si.
Figure 5.8 shows the mechanism by which channel stress could be induced
by the metal gate. In the strained-channel FinFET the metal gate electrode
tends to expand more than the SiN capping layer or the Si fin during the S/D
anneal. With the presence of the SiN capping layer, a limited expansion of
the TaN gate in the upward direction takes place and results in a compressive stress being exerted onto the Si fin, as illustrated in Figure 5.8(a). This
compressive stress in the channel can be retained even after the SiN capping
layer is removed. Figure 5.8(b) illustrates that due to the unique structure of
the FinFET device, a constrained expansion of the metal gates on both the
left and the right side of the fin effectively compresses or squeezes the fin on
at least two sides.
The I d -V d characteristics of a 75 nm gate length LG FinFET are shown in
Figure 5.9(a), with the current being normalised by two times the fin height
H fin . The strained-channel FinFET gives a significantly higher drive current
Strain-Engineered MOSFETs
and (110) side surfaces sitting on top of the buried oxide (BOX). A simplified process flow includes the active region, gate, contact, and metal
level patterning. The spacer, implant, and silicide process modules are
all self-aligned, as in standard planar CMOS processing. Tri-gate FinFET
devices have the following advantages: provide more drive current, work
in three dimensions, have a geometry advantage, and are fully depleted.
A high-performance tri-gate fully depleted CMOS with 60 nm physical
gate lengths has been demonstrated that exhibits lower leakage than a
standard planar CMOS.
Among the various approaches, introduction of stress by metal-nitride
gate is promising. It has been reported that fully silicided metal gate can
induce strain in the transistor channel, and the localised strain could be
exploited to enhance the performance of aggressively scaled transistors.
FinFET structures allow the use of low-channel dopant concentration, and
avoid problems associated with random dopant fluctuation. The threshold
voltage of FinFETs can be set through gate work function engineering
using metal gates, which additionally eliminate the gate depletion effect
and dopant penetration problem for improved drive current. For n-channel
FinFET devices, the optimal gate work function lies between the midgap
and the conduction band of Si, which necessitates the use of metal gates. A
simple and cost-effective technique used to incorporate strain in the channel region of FinFET devices has been reported [6]. It is shown that the
metal gate can affect the transistor performance through the stress developed during the fabrication process. However, gate work function tuning,
process integration, and compatibility with gate dielectric continue to be
the major challenges in metal gate technology development. Annealing
of a TaN gate electrode capped with a SiN layer leads to the exertion of
a compressive stress on the Si fin. This results in a significant enhancement of the drive current in n-channel FinFETs. Mesa-isolated n-channel
FinFETs with TaN gates were fabricated on SOI with a (001) surface and
45 nm thick Si.
Figure 5.8 shows the mechanism by which channel stress could be induced
by the metal gate. In the strained-channel FinFET the metal gate electrode
tends to expand more than the SiN capping layer or the Si fin during the S/D
anneal. With the presence of the SiN capping layer, a limited expansion of
the TaN gate in the upward direction takes place and results in a compressive stress being exerted onto the Si fin, as illustrated in Figure 5.8(a). This
compressive stress in the channel can be retained even after the SiN capping
layer is removed. Figure 5.8(b) illustrates that due to the unique structure of
the FinFET device, a constrained expansion of the metal gates on both the
left and the right side of the fin effectively compresses or squeezes the fin on
at least two sides.
The I d -V d characteristics of a 75 nm gate length LG FinFET are shown in
Figure 5.9(a), with the current being normalised by two times the fin height
H fin . The strained-channel FinFET gives a significantly higher drive current