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Strain-Engineered MOSFETs
from the drain bias, and in this way suppresses the short-channel effects.
The primary challenge in fabricating such structures is achieving satisfactory
self-alignment between the upper and lower gates. Advanced SOI MOSFETs
with thin body (thinner than 50% of L g ) thickness (T Si ) can suppress the leakage current, which makes this approach technically challenging. In doublegate architecture, the presence of two gates across an ultra-thin body (UTB)
helps to reduce the SCE and thus provide a better subthreshold slope. This
significantly reduces the subthreshold leakage current for a given I on . For
example, the DG device does not need to have high-channel doping to scale
because it is defined by body thickness, which is normally 50 to 70% of the
gate length to suppress the SCE effectively. As a result, mobility degradation and statistical dopant fluctuation problems can be eliminated. Similarly,
X j is also defined by the body thickness; thus, the shallow junction can be
realised relatively easily without developing complicated junction implantation techniques.
Many different methods have been proposed to fabricate DG devices, but
most of them suffer from technical challenges, mainly due to the process
complexity. For example, the vertical devices with pillar-like channels have
a large gate overlap capacitance, and the required processes are very complicated. Devices fabricated on ultra-thin silicon-on-insulator (SOI) wafer
(Figure 5.4(a)) are able to achieve a smaller I off by eliminating the leakage
path, which is far away from the gate control. When L g is scaled down to
less than 15 nm, according to the International Technology Roadmap
for Semiconductors, FinFET or a multigate device structure, as shown in
Figure 5.4(b), will be required to control the I off more effectively. As shown in
Figure 5.4(c), the drain current can flow from the source to the drain on the
top surface and on both sidewall surfaces of the fin. The surface orientations
are different, with the top surface being (100) and the sidewall surfaces being
(110). The mobility of the carriers traveling in the different surfaces will also
be different. For example, it is well known that the hole mobility is higher
on a (110) plane than on the (100) [4]. Multiple-gate transistor structures have
superior scalability over conventional planar metal-oxide-semiconductor
transistor structures, and enable gate length scaling well beyond the 32 nm
technology generation. The performance of the multigate device will depend
a lot on the dimension of the fin width (W fin ). Devices with smaller L g will
usually require smaller W fin for better SCE control. However, the decrease in
W fin is accompanied by an increase in series resistance, which degrades the
drive current.
FinFET is the most manufacturable double-gate (DG) structure due to
process compatibility with conventional planar bulk MOSFETs. However,
the channel surface (fin sidewall) roughness induced by photolithography
and dry etching degrades carrier mobilities without a subsequent surface
smoothening process. Advanced transistor structures such as multigate
field-effect transistors improve carrier mobilities further because a heavily
doped channel is not necessary to control short-channel effects, compared
Strain-Engineered MOSFETs
from the drain bias, and in this way suppresses the short-channel effects.
The primary challenge in fabricating such structures is achieving satisfactory
self-alignment between the upper and lower gates. Advanced SOI MOSFETs
with thin body (thinner than 50% of L g ) thickness (T Si ) can suppress the leakage current, which makes this approach technically challenging. In doublegate architecture, the presence of two gates across an ultra-thin body (UTB)
helps to reduce the SCE and thus provide a better subthreshold slope. This
significantly reduces the subthreshold leakage current for a given I on . For
example, the DG device does not need to have high-channel doping to scale
because it is defined by body thickness, which is normally 50 to 70% of the
gate length to suppress the SCE effectively. As a result, mobility degradation and statistical dopant fluctuation problems can be eliminated. Similarly,
X j is also defined by the body thickness; thus, the shallow junction can be
realised relatively easily without developing complicated junction implantation techniques.
Many different methods have been proposed to fabricate DG devices, but
most of them suffer from technical challenges, mainly due to the process
complexity. For example, the vertical devices with pillar-like channels have
a large gate overlap capacitance, and the required processes are very complicated. Devices fabricated on ultra-thin silicon-on-insulator (SOI) wafer
(Figure 5.4(a)) are able to achieve a smaller I off by eliminating the leakage
path, which is far away from the gate control. When L g is scaled down to
less than 15 nm, according to the International Technology Roadmap
for Semiconductors, FinFET or a multigate device structure, as shown in
Figure 5.4(b), will be required to control the I off more effectively. As shown in
Figure 5.4(c), the drain current can flow from the source to the drain on the
top surface and on both sidewall surfaces of the fin. The surface orientations
are different, with the top surface being (100) and the sidewall surfaces being
(110). The mobility of the carriers traveling in the different surfaces will also
be different. For example, it is well known that the hole mobility is higher
on a (110) plane than on the (100) [4]. Multiple-gate transistor structures have
superior scalability over conventional planar metal-oxide-semiconductor
transistor structures, and enable gate length scaling well beyond the 32 nm
technology generation. The performance of the multigate device will depend
a lot on the dimension of the fin width (W fin ). Devices with smaller L g will
usually require smaller W fin for better SCE control. However, the decrease in
W fin is accompanied by an increase in series resistance, which degrades the
drive current.
FinFET is the most manufacturable double-gate (DG) structure due to
process compatibility with conventional planar bulk MOSFETs. However,
the channel surface (fin sidewall) roughness induced by photolithography
and dry etching degrades carrier mobilities without a subsequent surface
smoothening process. Advanced transistor structures such as multigate
field-effect transistors improve carrier mobilities further because a heavily
doped channel is not necessary to control short-channel effects, compared