122
Strain-Engineered MOSFETs
introduced at the 45 nm CMOS technology node to replace the polysilicon
gate to enable oxide thickness scaling. p-MOSFET strain implementation
has the following features: (1) SiGe epitaxial S/D formed by Si recess etch
and selective strained SiGe epigrowth, (2) strained SiGe-induced large lateral compression in the channel, resulting in higher mobility, (3) SiGe S/D
improvement of parasitic resistance by reducing salicide interface resistance, and (4) strained SiGe having a smaller hole barrier height at the
silicide interface.
5.2 Multigate Transistors
The multiple-gate field-effect transistor is a promising device architecture
for the 45 nm CMOS technology node and beyond. Transition from the
planar bulk to the multigate architecture facilitates the target subthreshold performance while still keeping the channel doping concentration
low, if ultra-thin Si films and metal gates can be used to control SCEs and
adjust the threshold voltage, respectively. Multigate field-effect transistors include double-gate FinFETs, tri-gate FETs, omega-FETs, pi-gate FETs,
and gate-all-around FETs, which have been reported to achieve enhanced
performance with CMOS-compatible processing. Benefits of multigate
FETs include: (1) can harvest 20% more current per chip area, (2) better
subthreshold swing due to full depletion, (3) more resistant to random
dopant fluctuations, and (4) suppress stress proximity effects. However,
these nonplanar devices suffer from a high parasitic resistance due to the
narrow width of their source/drain (S/D) regions. The key operation differences and technological issues for each device type are summarised in
Table 5.1. Schematics of various types of multigate devices are shown in
Figure 5. 3.
Specific features of some of the devices are described below. In gateall-around (GAA) FETs the gate material surrounds the channel region on
all sides. The threshold voltage of GAA FETs is independent of substrate
bias due to the complete electrostatic shielding of the channel body. High
drive current, excellent gate control revealed by low SCE, and near-ideal subthreshold slope were demonstrated in these devices [3]. The vertical doublegate devices are in their nature modified tri-gate devices. The thick oxide
(hard mask) on top of the fin isolates the top gate electrode, and in this way
it offers an alternative solution to the “corner effect.” The concept of a tri-gate
device with sidewalls extending into the buried oxide (called a Π-gate) has
been proposed. The gate sidewall extensions effectively act as a back gate
through a lateral field effect in the buried oxide. The Π-gate device is simpler
to manufacture than the GAA and offers electrical characteristics and shortchannel properties close to those of GAA MOSFETs.
Strain-Engineered MOSFETs
introduced at the 45 nm CMOS technology node to replace the polysilicon
gate to enable oxide thickness scaling. p-MOSFET strain implementation
has the following features: (1) SiGe epitaxial S/D formed by Si recess etch
and selective strained SiGe epigrowth, (2) strained SiGe-induced large lateral compression in the channel, resulting in higher mobility, (3) SiGe S/D
improvement of parasitic resistance by reducing salicide interface resistance, and (4) strained SiGe having a smaller hole barrier height at the
silicide interface.
5.2 Multigate Transistors
The multiple-gate field-effect transistor is a promising device architecture
for the 45 nm CMOS technology node and beyond. Transition from the
planar bulk to the multigate architecture facilitates the target subthreshold performance while still keeping the channel doping concentration
low, if ultra-thin Si films and metal gates can be used to control SCEs and
adjust the threshold voltage, respectively. Multigate field-effect transistors include double-gate FinFETs, tri-gate FETs, omega-FETs, pi-gate FETs,
and gate-all-around FETs, which have been reported to achieve enhanced
performance with CMOS-compatible processing. Benefits of multigate
FETs include: (1) can harvest 20% more current per chip area, (2) better
subthreshold swing due to full depletion, (3) more resistant to random
dopant fluctuations, and (4) suppress stress proximity effects. However,
these nonplanar devices suffer from a high parasitic resistance due to the
narrow width of their source/drain (S/D) regions. The key operation differences and technological issues for each device type are summarised in
Table 5.1. Schematics of various types of multigate devices are shown in
Figure 5. 3.
Specific features of some of the devices are described below. In gateall-around (GAA) FETs the gate material surrounds the channel region on
all sides. The threshold voltage of GAA FETs is independent of substrate
bias due to the complete electrostatic shielding of the channel body. High
drive current, excellent gate control revealed by low SCE, and near-ideal subthreshold slope were demonstrated in these devices [3]. The vertical doublegate devices are in their nature modified tri-gate devices. The thick oxide
(hard mask) on top of the fin isolates the top gate electrode, and in this way
it offers an alternative solution to the “corner effect.” The concept of a tri-gate
device with sidewalls extending into the buried oxide (called a Π-gate) has
been proposed. The gate sidewall extensions effectively act as a back gate
through a lateral field effect in the buried oxide. The Π-gate device is simpler
to manufacture than the GAA and offers electrical characteristics and shortchannel properties close to those of GAA MOSFETs.