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Strain-Engineered MOSFETs
For scaled CMOS devices, a major drawback of midgap metals is that since
the band gap of Si is fixed at 1.1 eV, the threshold voltage for any midgap
metal on Si will be 0.5 V for both n- and p-MOSFETs. Since voltage supplies
are expected to be <1.0 V for sub-130 nm CMOS technology, a V th of 0.5 V is
much too large, as it would be difficult to turn on the device. Lowering of
the V th would require a lowering of the doping concentration, which would
degrade the short-channel characteristics. Therefore, the ideal situation
calls for two metals with dual work function: 4 eV for n-MOSFETs and 5 eV
for p-MOSFETs. This will enable low-threshold voltages without degraded
short-channel effects. For example, the work function value of Al could produce a V th of 0.2 V for NMOS, while the higher work function value of Pt
could achieve V th (0.2 V) for p-MOSFETs.
5.1.4 High-k Gate Dielectrics
The successful scaling of silicon-based CMOS technology has been attributed to the prevailing gate dielectric: silicon dioxide. Silicon dioxide exhibits excellent properties, such as remarkable interface quality and robust
reliability. However, as silicon dioxide thickness is scaled down, the gate
leakage current due to direct tunneling process increases exponentially. For
example, for silicon dioxide thinner than 4 nm, every 5 Å reduction in the
oxide thickness will result in about two orders of magnitude increase in
the direct tunneling current, in which the major challenge is the scaling of
the gate dielectric. Traditional gate dielectric, silicon dioxide, has touched
its fundamental limit for the 90 nm technology node because the tunneling current increases exponentially as the thickness of the gate dielectric
scales down. To continue the scaling trend of the gate dielectric, materials with high permittivity (high-k) have been intensively investigated as
possible replacements of silicon dioxide. Several high-k materials have been
shown to be promising, such as HfO 2 , but many critical integration issues
have to be solved for use in MOSFET technologies. As gate oxide thickness decreases, the capacitance associated with the depleted layer at the
poly-Si/gate dielectric interface becomes significant, making it necessary to
consider alternative gate electrodes. The search for metallic gates also faces
many challenges since they must have compatible work functions, thermal/
chemical interface stability with the underlying dielectric, and high carrier
concentration.
Intel has been at the forefront in addressing the above challenges by
successfully driving transistor innovations from the research phase to
mainstream CMOS manufacturing. Innovations introduced by Intel to
overcome traditional scaling limitations for n-MOSFETs are the following:
(1) uniaxial process-induced strain for mobility enhancement starting at
the 90 nm CMOS technology node, (2) epitaxial SiGe S/D (e-SiGe), (3) SiN
capping layers, (4) high-k gate dielectric introduced at the 45 nm CMOS
technology node to replace SiO 2 to reduce gate leakage, and (5) metal gate
Strain-Engineered MOSFETs
For scaled CMOS devices, a major drawback of midgap metals is that since
the band gap of Si is fixed at 1.1 eV, the threshold voltage for any midgap
metal on Si will be 0.5 V for both n- and p-MOSFETs. Since voltage supplies
are expected to be <1.0 V for sub-130 nm CMOS technology, a V th of 0.5 V is
much too large, as it would be difficult to turn on the device. Lowering of
the V th would require a lowering of the doping concentration, which would
degrade the short-channel characteristics. Therefore, the ideal situation
calls for two metals with dual work function: 4 eV for n-MOSFETs and 5 eV
for p-MOSFETs. This will enable low-threshold voltages without degraded
short-channel effects. For example, the work function value of Al could produce a V th of 0.2 V for NMOS, while the higher work function value of Pt
could achieve V th (0.2 V) for p-MOSFETs.
5.1.4 High-k Gate Dielectrics
The successful scaling of silicon-based CMOS technology has been attributed to the prevailing gate dielectric: silicon dioxide. Silicon dioxide exhibits excellent properties, such as remarkable interface quality and robust
reliability. However, as silicon dioxide thickness is scaled down, the gate
leakage current due to direct tunneling process increases exponentially. For
example, for silicon dioxide thinner than 4 nm, every 5 Å reduction in the
oxide thickness will result in about two orders of magnitude increase in
the direct tunneling current, in which the major challenge is the scaling of
the gate dielectric. Traditional gate dielectric, silicon dioxide, has touched
its fundamental limit for the 90 nm technology node because the tunneling current increases exponentially as the thickness of the gate dielectric
scales down. To continue the scaling trend of the gate dielectric, materials with high permittivity (high-k) have been intensively investigated as
possible replacements of silicon dioxide. Several high-k materials have been
shown to be promising, such as HfO 2 , but many critical integration issues
have to be solved for use in MOSFET technologies. As gate oxide thickness decreases, the capacitance associated with the depleted layer at the
poly-Si/gate dielectric interface becomes significant, making it necessary to
consider alternative gate electrodes. The search for metallic gates also faces
many challenges since they must have compatible work functions, thermal/
chemical interface stability with the underlying dielectric, and high carrier
concentration.
Intel has been at the forefront in addressing the above challenges by
successfully driving transistor innovations from the research phase to
mainstream CMOS manufacturing. Innovations introduced by Intel to
overcome traditional scaling limitations for n-MOSFETs are the following:
(1) uniaxial process-induced strain for mobility enhancement starting at
the 90 nm CMOS technology node, (2) epitaxial SiGe S/D (e-SiGe), (3) SiN
capping layers, (4) high-k gate dielectric introduced at the 45 nm CMOS
technology node to replace SiO 2 to reduce gate leakage, and (5) metal gate