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Strain-Engineered MOSFETs
Recently there has been a great deal of interest in channel engineering
through the introduction of local stress. Both the SiGe and SiC have been used
in the source/drain regions to introduce stress locally for device drive current enhancement. Intel first introduced the new hafnium-based dielectrics
with metal gates for its 45 nm technology node. Together with new dielectric
and metal gates, an improved technique to induce more strain into the channel for obtaining enhanced performance was employed for the 22 nm technology node. Toward performance enhancement, the CMOS technology will
utilise various approaches, such as advanced MOSFET structures, metal gate
with tunable work function, strained Si, and channel orientation optimisation. In addition to these process-based solutions to control SCE for scaled
device dimensions, there exist fundamental limitations on device size that
will be addressed in the following sections. The objective of this chapter is
performance evaluation and prediction for nanoscale devices in silicon technology beyond the 45 nm CMOS technology node.
5.1 Process Integration
As discussed above, some of the main challenges faced by the Si CMOS technology are large short-channel effects resulting in an exponential increase
in leakage power, process variations resulting in large deviations in the performance of the circuits, and technological limitations. Leakage power is
broadly classified into two categories: standby leakage, which corresponds
to the situation when the circuit is in a nonoperating or sleep mode, and
active leakage, which relates to leakage during normal operation. Technology
boosters such as strain have helped the continuation of CMOS historic performance trend up to the 45 nm node. Process integration challenges are (1)
power consumption, (2) leakage current, (3) metal gate electrodes, and (4)
high-k gate dielectrics, which are discussed below.
5.1.1 Power Consumption
As transistor sizes shrink, the total power consumption of chips is becoming a dominant factor in determining the chip performance. The power
consumption of microprocessor cores and interconnects constitutes a significant portion of the total power consumption of modern microprocessors.
Leakage current is a primary concern for low-power, high-performance digital CMOS circuits for portable applications, and industry trends show that
leakage will be the dominant component of power in future technologies.
According to the International Technological Roadmap for Semiconductors,
physical oxide thickness (T ox ) values of 7–12 Å will be required for highperformance CMOS circuits, and quantum effects that cause tunneling will
Strain-Engineered MOSFETs
Recently there has been a great deal of interest in channel engineering
through the introduction of local stress. Both the SiGe and SiC have been used
in the source/drain regions to introduce stress locally for device drive current enhancement. Intel first introduced the new hafnium-based dielectrics
with metal gates for its 45 nm technology node. Together with new dielectric
and metal gates, an improved technique to induce more strain into the channel for obtaining enhanced performance was employed for the 22 nm technology node. Toward performance enhancement, the CMOS technology will
utilise various approaches, such as advanced MOSFET structures, metal gate
with tunable work function, strained Si, and channel orientation optimisation. In addition to these process-based solutions to control SCE for scaled
device dimensions, there exist fundamental limitations on device size that
will be addressed in the following sections. The objective of this chapter is
performance evaluation and prediction for nanoscale devices in silicon technology beyond the 45 nm CMOS technology node.
5.1 Process Integration
As discussed above, some of the main challenges faced by the Si CMOS technology are large short-channel effects resulting in an exponential increase
in leakage power, process variations resulting in large deviations in the performance of the circuits, and technological limitations. Leakage power is
broadly classified into two categories: standby leakage, which corresponds
to the situation when the circuit is in a nonoperating or sleep mode, and
active leakage, which relates to leakage during normal operation. Technology
boosters such as strain have helped the continuation of CMOS historic performance trend up to the 45 nm node. Process integration challenges are (1)
power consumption, (2) leakage current, (3) metal gate electrodes, and (4)
high-k gate dielectrics, which are discussed below.
5.1.1 Power Consumption
As transistor sizes shrink, the total power consumption of chips is becoming a dominant factor in determining the chip performance. The power
consumption of microprocessor cores and interconnects constitutes a significant portion of the total power consumption of modern microprocessors.
Leakage current is a primary concern for low-power, high-performance digital CMOS circuits for portable applications, and industry trends show that
leakage will be the dominant component of power in future technologies.
According to the International Technological Roadmap for Semiconductors,
physical oxide thickness (T ox ) values of 7–12 Å will be required for highperformance CMOS circuits, and quantum effects that cause tunneling will